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參數(shù)資料
| 型號(hào)： | DG613DY-T1-E3 |
| 廠商： | Vishay Siliconix |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 0K |
| 描述： | IC SWITCH QUAD NO/NC 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 開關(guān) |
| 電路： | 1 x DPDT |
| 導(dǎo)通狀態(tài)電阻： | 45 歐姆 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 10 V ~ 18 V，±10 V ~ 15 V |
| 電流 - 電源： | -1µA，1µA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | DG613DY-T1-E3DKR |
Vishay Siliconix
DG611, DG612, DG613
Document Number: 70057
S11-0154-Rev. I, 31-Jan-11
www.vishay.com
1
High-Speed, Low-Glitch D/CMOS Analog Switches
FEATURES
Fast switching - tON: 12 ns
Low charge injection: ± 2 pC
Wide bandwidth: 500 MHz
5 V CMOS logic compatible
Low RDS(on): 18
Low quiescent power : 1.2 nW
Single supply operation
BENEFITS
Improved data throughput
Minimal switching transients
Improved system performance
Easily interfaced
Low insertion loss
Minimal power consumption
APPLICATIONS
Fast sample-and-holds
Synchronous demodulators
Pixel-rate video switching
Disk/tape drives
DAC deglitching
Switched capacitor filters
GaAs FET drivers
Satellite receivers
DESCRIPTION
The DG611, DG612, DG613 feature high-speed low-
capacitance lateral DMOS switches. Charge injection has
been minimized to optimize performance in fast sample-and-
hold applications.
Each switch conducts equally well in both directions when on
and blocks up to 16 Vp-p when off. Capacitances have been
minimized to ensure fast switching and low-glitch energy. To
achieve such fast and clean switching performance, the
DG611, DG612, DG613 are built on the Vishay Siliconix
proprietary D/CMOS process. This process combines
n-channel DMOS switching FETs with low-power CMOS
control logic and drivers. An epitaxial layer prevents latchup.
The DG611 and DG612 differ only in that they respond to
opposite logic levels. The versatile DG613 has two normally
open and two normally closed switches. It can be given
various configurations, including four SPST, two SPDT, one
DPDT.
For additional information see Applications Note AN207.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Four SPST Switches per Package
Logic “0”
1 V
Logic “1”
4 V
* Pb containing terminations are not RoHS compliant, exemptions may apply
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
IN1
IN2
D1
D2
S1
S2
V-
V+
GND
VL
S4
S3
D4
D3
IN4
IN3
Dual-In-Line
and SOIC
DG611
Top View
S1
S2
V-
V+
NC
GND
VL
S4
S3
LCC
NC IN3 D3
D4 IN4
NC IN2 D2
D1 IN1
Key
910
11
12
13
4
5
6
7
8
1
2
319
20
14
15
16
17
18
DG611
TRUTH TABLE
Logic
DG611
DG612
0
ON
OFF
1OFF
ON
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