參數(shù)資料
型號: DG506BEW-T1-GE3
廠商: Vishay Siliconix
文件頁數(shù): 14/17頁
文件大?。?/td> 0K
描述: IC MUX ANA DUAL 16/8CH 28SOIC
標準包裝: 1,500
功能: 多路復(fù)用器
電路: 1 x 16:1
導(dǎo)通狀態(tài)電阻: 450 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 12V,±15V
電流 - 電源: 100µA
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC
包裝: 帶卷 (TR)
Vishay Siliconix
DG506B, DG507B
www.vishay.com
6
Document Number: 65150
S13-2567-Rev. C, 16-Dec-13
This document is subject to change without notice.
THE PRODUCT DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: analogswitchtechsupport@vishay.com
Notes:
a. VAX, VEN = input voltage perform proper function.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet.
e. Guaranteed by design, not subject to production test.
f.
R
DS(on) = RDS(on) max. - RDS(on) min.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SCHEMATIC DIAGRAM Typical Channel
Dynamic Characteristics
Source Off Capacitancee
CS(off)
f = 1 MHz
Room
4
pF
Drain Off Capacitancee
CD(off)
DG506B
37
DG507B
20
Channel On Capacitancee
CD(on)
DG506B
43
DG507B
26
Power Supply
Power Supply Current
I+
VAX, VEN = 0 V, or 5 V
Room
0.005
0.1
mA
Full
0.1
SPECIFICATIONS Single Supply 12 V
Parameter
Symbol
Test Conditions
Unless Otherwise Specified
V+ = 12 V, V- = 0 V (± 10 %)
VAX, VEN = 2.4 V, 0.8 V
a
Temp.b
Typ.c
A Suffix
-40 °C to 125 °C
D Suffix
-40 °C to 85 °C
Unit
Min.d
Max.d
Min.d
Max.d
Figure 1.
EN
A0
S1
D
Sn
Decode/
Drive
Level
Shift
V-
V+
V-
VREF
AX
GND
V-
V+
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