參數(shù)資料
型號(hào): DG485
廠商: Vishay Intertechnology,Inc.
英文描述: Octal Analog Switch Array(8通道模擬多路轉(zhuǎn)換器(由8個(gè)單刀單擲模擬開關(guān)和一個(gè)通用輸出組成))
中文描述: 八路模擬開關(guān)陣列(8通道模擬多路轉(zhuǎn)換器(由8個(gè)單刀單擲模擬開關(guān)和一個(gè)通用輸出組成))
文件頁數(shù): 1/11頁
文件大?。?/td> 85K
代理商: DG485
DG485
Vishay Siliconix
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com
1
Octal Analog Switch Array
Low On-Resistance: 55
Rail-to-Rail Analog Input Range
Serial Interface
Low-Power—P
D
: 35 nW
TTL and CMOS Compatible
Any Combination of 8 SPST to the
Output
High Speed—t
ON
: 170 ns
Low Signal Distortion
Devices Can Be Chained for System
Expansion
Reduced Board Space
Reduced Switch Errors
Reduced Power Supply
Requirements
Simple Interfacing
Audio Switching and Routing
Audio Teleconferencing
Data Acquisition and Industrial
Process Control
Battery Powered Remote Systems
Automotive, Avionics and ATE
Systems
Summing Amplifiers
The DG485 is an analog switch array consisting of eight SPST
switches connected to a common output. This device may be
used as an 8-channel multiplexer in serial control applications.
Any, all or none of the eight switches may be closed at any
given time. Combining low on-resistance (r
DS(on)
55
and fast switching (t
ON
: 170 ns, typ.), the DG485 is ideally
suited for data acquisition, process control, communication,
and avionic applications.
, typ.)
Control data is input serially into the shift register with each
clock pulse. The shift register contents can be latched-in (via
LD) at any point into an octal latch which in turn controls all
switches. RS resets the shift register, forcing all latch inputs
to a low condition (all switches off). The serial input (D
IN
) and
serial output (D
OUT
) allow daisy chaining of multiple arrays for
large systems.
Built on the Vishay Siliconix high voltage silicon gate process
the DG485 has a wide 44-V power supply voltage rating. An
epitaxial layer prevents latchup.
Each channel conducts equally well in either direction when on
and blocks up to rail-to-rail voltages when off.
For additional information please refer to application note
AN204.
1
2
3
4
5
6
7
8
18
17
16
15
14
13
12
11
LD
RS
V
L
GND
S
4
D
S
3
S
5
S
2
S
6
S
1
S
7
V+
S
8
D
IN
V–
Dual-In-Line
Top View
9
10
CLK
D
OUT
Shift Register
Latches
PLCC and LCC
14
15
16
17
18
8
7
6
5
4
1
2
3
19
20
11
10
9
13
12
Top View
S
4
D
S
3
S
5
S
6
S
2
S
1
S
7
V+
S
8
I
D
C
N
O
V
L
N
R
G
Shift Register/Latches
L
V
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