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參數(shù)資料
| 型號： | DG3157DL-T1-GE3 |
| 廠商： | Vishay Siliconix |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DECODER/DEMUX HS 2:1 SC70-6 |
| 標準包裝： | 3,000 |
| 功能： | 開關(guān) |
| 電路： | 1 x SPDT |
| 導(dǎo)通狀態(tài)電阻： | 15 歐姆 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-TSSOP，SC-88，SOT-363 |
| 供應(yīng)商設(shè)備封裝： | SC-70-6 |
| 包裝： | 帶卷 (TR) |
Document Number: 72648
S09-0294-Rev. D, 23-Feb-09
www.vishay.com
3
Vishay Siliconix
DG3157
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for design aid only, not guaranteed nor subject to production testing.
d. Guarantee by design, nor subjected to production test.
e. VIN = input voltage to perform proper function.
f. Guaranteed by design and not production tested. The bus switch propagation delay is a function of the RC time constant contributed by the
on-resistance and the specified load capacitance with an ideal voltage source (zero output impedance) driving the switch.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
Parameter
Symbol
Test Conditions
Unless Otherwise Specified
V+ = 3.0 V, VS = 0.25 V to 0.7 V+
e
Temp.a
Limits
- 40 °C to 85 °C
Unit
Min.b
Typ.c
Max.b
Power Supply
Power Supply Range
V+
Full
1.65
5.5
V
Quiescent Supply Current
I+
V+ = 5.5 V, VA = VB = V+ or GND
Room
Full
1
10
A
AC Electrical Characteristice
Prop Delay Timef
tPHL/tPLH
VA = 0 V
V+ = 1.65 to 1.95 V
Full
ns
V+ = 2.3 to 2.7 V
Full
1.2
V+ = 3.0 to 3.6 V
Full
0.8
V+ = 4.5 to 5.5 V
Full
0.3
Output Enable Timef
tPZL/tPZH
VLOAD = 2 x V+ for tPZL
VLOAD = 0 V for tPZH
V+ = 1.65 to 1.95 V
Room
Full
10.2
10.4
V+ = 2.3 to 2.7 V
Room
Full
5.9
6.2
V+ = 3.0 to 3.6 V
Room
Full
4.1
4.5
V+ = 4.5 to 5.5 V
Room
Full
2.6
2.9
Output Disable Timef
tPLZ/tPHZ
VLOAD = 2 x V+ for tPLZ
VLOAD = 0 V for tPHZ
V+ = 1.65 to 1.95 V
Room
Full
10.2
10.4
V+ = 2.3 to 2.7 V
Room
Full
5.9
6.2
V+ = 3.0 to 3.6 V
Room
Full
4.1
4.5
V+ = 4.5 to 5.5 V
Room
Full
2.6
2.9
Break-Before-Make Timed
tBBM
V+ = 1.65 to 1.95 V
Full
0.5
V+ = 2.3 to 2.7 V
Full
0.5
V+ = 3.0 to 3.65
Full
0.5
V+ = 4.5 to 5.5 V
Full
0.5
Charge Injectiond
Q
CL = 0.1 nF, VGEN = 0 V
RGEN = 0 Ω
V+ = 5 V
Room
7
pC
V+ = 3.3 V
Room
3
Analog Switch Characteristics
Off Isolationd
OIRR
RL = 50 Ω, f = 10 MHz
Room
- 57.6
dB
Crosstalkd
XTALK
Room
- 58.7
- 3 db Bandwidthd
BW
RL = 50 Ω
Room
> 250
MHz
Capacitance
Control Pin Capacitanced
CIN
V+ = 0 V
Room
4.9
pF
B Port Off Capacitanced
CIO-B
V+ = 5 V
Room
< 6.5
A Port Capacitance When
Switch Enabled
CIO-A(on)
Room
< 18.5
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