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參數(shù)資料
| 型號(hào)： | DEM-ADS7833 |
| 英文描述： | DEM-ADS7833 - EVALUATION FIXTURE |
| 中文描述： | DEM的ADS7833 -評(píng)價(jià)夾具 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 206K |
| 代理商： | DEM-ADS7833 |
4
DEM-ACF2101BP
Hold
Sw In
Reset
Hold
Reset
Select
Cap
In
Com
Sw Com
Sw Out
Out
100pF
C
INT
FIGURE 3. Block Diagram of 1/2 of the ACF2101BP.
MODES OF OPERATION
O
0
–10
OFF
ON
OFF
ON
HOLD
RESET
INTEGRATE
HOLD RST HOLD INTEGRATE
HOLD
Cycle
Time
MODE OF OPERATION
INTEGRATE
SWITCH
HOLD
RESET
Hold Switch
Reset Switch
On
Off
Off
Off
On/Off
On
voltage coefficient, temperature coefficient, memory, and
leakage current. Suitable types include NPO ceramic, poly-
carbonate, polystyrene, and silver mica. Space for an exter-
nal integration capacitor (C
2
and C
5
) is also provided on the
board.
The SW OUT of both channels are connected to operational
amplifiers configured as buffers (U6). A space for an output
hold capacitor (C
6
and C
7
) is provided on the board for each
side of the dual ACF2101BP. An example of how C
6
and C
7
could be used with the help of the OPA2107 (U6) opera-
tional amplifier is shown in Figure 5. In Figure 5, the
ACF2101BP is used as a programmable current to voltage
converter. The output of the circuit, V
OUT
is a dc level for a
constant current input. Refer to the ACF2101 data sheet
(PDS-1078) for a detailed discussion of this application.
By changing R
and R
from zero ohm (factory configured)
jumpers to resistors, a voltage source can be integrated
instead of a current source as shown in the schematic in
Figure 6. C
and C
must be added to the circuit in this
application to prevent the voltage at SW IN A and SW IN B
from exceeding +0.5V when the HOLD switch is off (or
open). If the voltage at SW IN A or SW IN B exceeds +0.5V,
the protection circuitry will begin to conduct. This will not
damage the ACF2101BP, but performance specifications
will not be met. Selection of C
and C
is dependent on the
time that the ACF2101BP is in the hold mode and the
magnitude of i
IN
.
C
3
, C
4
≥
(t
HOLD
i
IN(max)
) / 0.5V
t
= time that the ACF2101BP is in the hold mode
(seconds)
i
IN(MAX)
= maximum expected input current (amperes)
C
3
, C
4
= capacitance (farads)
PROGRAMMABLE TIMING GENERATOR
The timing generator (Figure 7) provides the RESET,
SELECT, and HOLD control signals for the operation of the
ACF2101. This generator is a programmable state machine
that consist of a decade counter and a few flip-flops. Each
ACF2101 control signal has its own edge-triggered flip-flop.
FIGURE 4. Modes of Operation of the ACF2101.
FIGURE 5. Block Diagram of a Programmable Current-to-Voltage Converter using the DEM-ACF2101BP Evaluation Fixture.
On: Switch shorted; Logic 0 input. Off: Switch open; Logic 1 input.
Hold
Reset
100pF
1/2
ACF2101
Select
V
OUT
I
SENSOR
C
IN
10nF
1/2
OPA2107
C
6
or C
7
Sensor
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