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| 型號： | DECIMATE |
| 廠商： | Intersil Corporation |
| 英文描述： | DECIMATE⑩ |
| 中文描述： | 毀滅⑩ |
| 文件頁數(shù)： | 2/5頁 |
| 文件大?。?/td> | 48K |
| 代理商： | DECIMATE |
2
contents. The user selects the step size of the input sample
clock and also selects the probes to be monitored. The
simulator will then clock through the specified number of
clock cycles and display the resulting time domain response.
Figure 5 shows a typical probe display.
Monarch 2.0 DSP Design Software
DECIMATE is fully integrated with Monarch 2.0 professional
DSP design software. Monarch is a full featured DSP
package with FIR lIR filter design and analysis, two
dimensional and three dimensional viewing, a
programmable signal/systems laboratory with 100 +
DSP/Math functions, extensive fixed-point support and
FFTs/IFETs Monarch is available separately from The
Athena Group, Inc.
When used with Monarch 2.0, DECIMATE becomes a full
feature design environment for a DSP system. Data can
easily be transferred from DECIMATE modules to the
Monarch modules for further analysis.
System Requirements
IBM PC, XT, AT, PS/2 computer or 100% compatible
with 640K RAM running MS/PC-DOS 2.0 or higher One
MegaByte of fixed-disk space with 5.25” or 3.5” floppy drive.
CGA, MCGA, EGA, VGA, 8514, or Hercules Graphics
Adapter. A Math coprocessor is strongly recommended.
S
DESIGN MODULE
SIMULATOR MODULE
PROM MODULE
Filter File
Input Sample Rate
Output Rate
Passband
Transition Band
Passband Atten
Stopband Atten
HSP43220 DDF FILTER SPECIFICATION
PRES.DDF
MHz
kHz
kHz
Hz
dB
dB
Design Mode
Generate Report
Display Response
Save Freq Responses
Save FIR Response
AUTO
YES
LOG
YES
YES
D
E
C
I
M
A
T
E
FIR Type
STANDARD
HDF Order
HDF Decimation
HDF Scale Factor
4
330
0.6903
FIR Input Rate
FIR Clock (min)
FIR Order
FIR Decimation
100
33
509
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
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FIGURE 1. FILTER SPECIFICATION MENU
:
33
100
5
700
1
96
kHz
MHz
DECIMATE
IBM PC, XT, AT, PS/2 are trademarks of IBM Corporation.
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