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參數(shù)資料
| 型號(hào)： | DDU8C3-5100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| 中文描述： | 5，技術(shù)咨詢，3.3V CMOS閾值接口固定延遲線 |
| 文件頁數(shù)： | 2/4頁 |
| 文件大?。?/td> | 45K |
| 代理商： | DDU8C3-5100 |
DDU8C3
Doc #00115
5/19/00
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 www.datadelay.com
2
APPLICATION NOTES
HIGH FREQUENCY RESPONSE
The DDU8C3 tolerances are guaranteed for input
pulse widths and periods greater than those
specified in the test conditions. Although the
device will function properly for pulse widths as
small as 40% of the total delay and periods as
small as 80% of the total delay (for a symmetric
input), the delays may deviate from their values at
low frequency. However, for a given input
condition, the deviation will be repeatable from
pulse to pulse. Contact technical support at Data
Delay Devices if your application requires device
testing at a specific input condition.
POWER SUPPLY BYPASSING
The DDU8C3 relies on a stable power supply to
produce repeatable delays within the stated
tolerances. A 0.1uf capacitor from VDD to GND,
located as close as possible to the VDD pin, is
recommended. A wide VDD trace and a clean
ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-55
MAX
7.0
V
DD
+0.3
150
300
UNITS
V
V
C
C
NOTES
10 sec
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.00V to 3.60V)
PARAMETER
High Level Output Voltage
SYMBOL
V
OH
MIN
3.00
TYP
3.20
MAX
UNITS
V
NOTES
V
DD
= 3.3, I
OH
= MAX
V
IH
= MIN, V
IL
= MAX
V
DD
= 3.3, I
OL
= MAX
V
IH
= MIN, V
IL
= MAX
Low Level Output Voltage
V
OL
0.10
0.30
V
High Level Output Current
Low Level Output Current
High Level Input Voltage
Low Level Input Voltage
Input Current
I
OH
I
OL
V
IH
V
IL
I
IH
-24.0
24.0
mA
mA
V
V
μ
A
2.50
0.80
0.10
V
DD
= 3.3
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| DDU8C3-5125 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5150 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5175 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5200 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDU8C3-5125 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5150 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5175 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5200 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
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