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參數(shù)資料
| 型號(hào)： | DDU8C-5050 |
| 英文描述： | Tapped Delay Line |
| 中文描述： | 抽頭延遲線 |
| 文件頁(yè)數(shù)： | 4/4頁(yè) |
| 文件大?。?/td> | 68K |
| 代理商： | DDU8C-5050 |
DDU8C
Doc #97013
DATA DELAY DEVICES, INC.
4
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DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (VDD):
5.0V
±
0.1V
Input Pulse:
OUTPUT:
Load:
C
load
:
Threshold:
1 FAST-TTL Gate
5pf
±
10%
2.5V (Rising & Falling)
High = 5.0V
±
0.1V
Low = 0.0V
±
0.1V
50
Max.
5.0 ns Max. (measured
between 0.5V and 4.5V )
PW
IN
= 1.5 x Total Delay
PER
IN
= 10 x Total Delay
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
T1
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
TIME INTERVAL
COUNTER
PULSE
GENERATOR
COMPUTER
SYSTEM
PRINTER
IN
T2
T3
T4
T5
0.5V
0.5V
Timing Diagram For Testing
T
RISE
T
FALL
PER
IN
PW
IN
T
RISE
T
FALL
4.5V
2.5V
2.5V
2.5V
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DDU8C-5050A1 | Delay Line |
| DDU8C-5050B1 | Delay Line |
| DDU8C3 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5004 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
| DDU8C3-5006 | 5-TAP, 3.3V CMOS-INTERFACED FIXED DELAY LINE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDU8C-5050A1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| DDU8C-5050B1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| DDU8C-5050M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| DDU8C-5050MD1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
| DDU8C-5050MD4 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Delay Line |
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