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參數(shù)資料
| 型號： | DDU4C3-5400 |
| 英文描述： | Logic IC |
| 中文描述： | 邏輯IC |
| 文件頁數(shù)： | 4/4頁 |
| 文件大?。?/td> | 65K |
| 代理商： | DDU4C3-5400 |
DDU4C
Doc #97034
12/10/97
DATA DELAY DEVICES, INC.
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (VDD):
5.0V
±
0.1V
Input Pulse:
OUTPUT:
Load:
C
load
:
Threshold:
1 FAST-TTL Gate
5pf
±
10%
2.5V (Rising & Falling)
High = 5.0V
±
0.1V
Low = 0.0V
±
0.1V
50
Max.
5.0 ns Max. (measured
between 0.5V and 4.5V )
PW
IN
= 1.5 x Total Delay
PER
IN
= 10 x Total Delay
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
T1
OUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
TIME INTERVAL
COUNTER
PULSE
GENERATOR
COMPUTER
SYSTEM
PRINTER
IN
T2
T3
T4
T5
0.5V
0.5V
Timing Diagram For Testing
T
RISE
T
FALL
PER
IN
PW
IN
T
RISE
T
FALL
4.5V
2.5V
2.5V
2.5V
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DDU4C3-5500 | Logic IC |
| DDU-4C-5175 | Tapped Delay Line |
| DDU4C-5050 | 5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C) |
| DDU4C-5060 | 5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C) |
| DDU4C-5075 | 5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DDU4C3-5500 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| DDU4C-5050 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C) |
| DDU4C-5050A2 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C) |
| DDU4C-5050B2 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C) |
| DDU4C-5050M | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:5-TAP, HCMOS-INTERFACED FIXED DELAY LINE (SERIES DDU4C) |
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