參數(shù)資料
型號: DDU37F-80M
廠商: DATA DELAY DEVICES INC
元件分類: 通用總線功能
英文描述: MECHANICALLY VARIABLE TTL DELAY LINE
中文描述: ACTIVE DELAY LINE, TRUE OUTPUT, DIP5
文件頁數(shù): 3/3頁
文件大?。?/td> 43K
代理商: DDU37F-80M
DDU37F
Doc #01016
11/12/01
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
Input Pulse:
OUTPUT:
Load:
C
load
:
Threshold:
1 FAST-TTL Gate
5pf
±
10%
1.5V (Rising & Falling)
5.0V
±
0.1V
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
50
Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PW
IN
= 1.5 x Total Delay
PER
IN
= 10 x Total Delay
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
IN
OUT
OUT
TRIG
IN
TRIG
Test Setup
DEVICE UNDER
TEST (DUT)
OSCILLOSCOPE
PULSE
GENERATOR
Timing Diagram For Testing
D
RISE
D
FALL
PER
IN
PW
IN
T
RISE
T
FALL
0.6
0.6
2.4
1.5
1.5
1.5
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
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