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參數(shù)資料
| 型號： | DDC112 |
| 英文描述： | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 雙路電流輸入20位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 210K |
| 代理商： | DDC112 |
16
DDC112
FIGURE 16. Equivalent CONV Signals in Non-Continuous Mode.
FIGURE 17. Non-Continuous Mode Timing with a 50% Duty Cycle CONV Signal.
CONV1
CONV2
2
3
1
3
4
4
1
2
State
mbsy
CONV
DVALID
2
3
1
3
4
4
1
State
Integration
Status
mbsy
Int B
Int A
Int B
Side A
Data
Side B
Data
Side A
Data
Int A
Looking at the state diagram, one can see that the CONV
pattern needed to generate a given state progression is not
unique. Upon entering states 1 or 8, the DDC112 remains in
those states until mbsy goes LOW, independent of CONV.
As long as the m/r/az cycle is underway, the state machine
ignores CONV (see Figure 9). The top two signals are
different CONV patterns that produce the same state.
This feature can be a little confusing at first, but it does
allow flexibility in generating ncont mode CONV patterns.
For example, the DDC112 Evaluation Fixture operates in
the ncont mode by generating a square wave with pulse
width < t
6
. Figure 17 illustrates operation in the ncont mode
using a 50% duty cycle CONV signal with T
INT
= 1620
CLK periods. Care must be exercised when using a square
wave to generate CONV. There are certain integration
times that must be avoided since they produce very short
intervals for state 2 (or state 7 if CONV is inverted). As seen
in the state diagram, the state progresses from 2 to 3 as soon
as CONV is HIGH. The state machine does not insure that
the duration of state 2 is long enough to properly prepare the
next side for integration (t
11
). This must be done by the user
with proper timing of CONV. For example, if CONV is a
square wave with T
INT
= 3042 CLK periods, state 2 will
only be 18 CLK periods long, therefore, t
11
will not be met.
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| DDC112U | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| DDC112UK | Dual Current Input 20-Bit ANALOG-TO-DIGITAL CONVERTER |
| DDC118 | Octal Current Input 20-Bit Analog-To-Digital Converter |
| DDC118IRTCR | Octal Current Input 20-Bit Analog-To-Digital Converter |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DDC1128ZKLT | 功能描述:20 Bit Analog to Digital Converter 128 Input 1 Sigma-Delta 192-NFBGA (9x9) 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 位數(shù):20 采樣率（每秒）:6.25k 輸入數(shù):128 輸入類型:單端 數(shù)據(jù)接口:SPI 配置:ADC 無線電 - S/H:ADC:- A/D 轉(zhuǎn)換器數(shù):1 架構:三角積分 參考類型:外部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:2.7 V ~ 3.6 V 特性:同步采樣 工作溫度:0°C ~ 70°C 封裝/外殼:192-LFBGA 供應商器件封裝:192-NFBGA（9x9） 標準包裝:1 |
| DDC112U | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Dual Current Input 20-Bit RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| DDC112U | 制造商:Texas Instruments 功能描述:20BIT ADC DUAL 3KHZ SOIC28 112 制造商:Texas Instruments 功能描述:20BIT ADC, DUAL, 3KHZ, SOIC28, 112 制造商:Texas Instruments 功能描述:20BIT ADC, DUAL, 3KHZ, SOIC28, 112; Resolution (Bits):20bit; Sampling Rate:3kSPS; Supply Voltage Type:Single; Supply Voltage Min:4.75V; Supply Voltage Max:5.25V; Supply Current:14.8mA; Digital IC Case Style:SOIC; No. of Pins:28; ;RoHS Compliant: Yes |
| DDC112U | 制造商:Texas Instruments 功能描述:20BIT ADC DUAL SMD SOIC28 112 |
| DDC112U | 制造商:Texas Instruments 功能描述:DUAL CURRENT INPUT 20 BIT ANALOG/DIGITAL |
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