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DUAL OUTPUT VOLTAGE DCP AND DCVs
The voltage output for the dual DCPs is half wave
rectified; therefore, the discharge time is 1.25
μ
s.
Repeating the above calculations using the 100%
load resistance of 25
(0.2A per output), the results
are:
τ
= 25
μ
s
t
DIS
= 1.25
μ
s
V
DIS
= 244mV
V
ESR
= 20mV
Ripple Voltage = 266mV
Ripple and Noise
PCB LAYOUT
Figure 11
and
Figure 12
illustrate a printed circuit
board
(PCB)
layout
for
(DCP01/02, DCV01), and two SO-28 surface-mount
packages
(DCP02U).
Figure
schematic.
THERMAL MANAGEMENT
Because of the high power density of this device, it is
advisable to provide ground planes on the input and
output.
SBVS011E–MARCH 2000–REVISED AUGUST 2006Clearly, increasing the capacitance has a much
smaller effect on the output ripple voltage than does
reducing the value of the ESR for the filter capacitor.
The SYNC
IN
pin, when not being used, is best left as
a floating pad. A ground ring or annulus connected
around the pin prevents noise being conducted onto
the pin. If the SYNC
IN
pin is to be connected to one
or more SYNC
IN
pins, then the linking trace should
be narrow and must be kept short in length. In
addition, no other trace should be in close proximity
to this trace because that will increase the stray
capacitance
on
this
pin.
capacitance affects the performance of the oscillator.
In
turn,
the
stray
Careful consideration should be given to the layout
of the PCB, in order to obtain the best results.
The DCP02 is a switching power supply, and as
such can place high peak current demands on the
input supply. In order to avoid the supply falling
momentarily during the fast switching pulses, ground
and power planes should be used to connect the
power to the input of DCP02. If this connection is not
possible, then the supplies must be connected in a
star formation with the traces made as wide as
possible.
This time, it is the capacitor discharging that
contributes to the largest component of ripple.
Changing the output filter to 10
μ
F, and repeating the
calculations, the result is:
Ripple Voltage = 45mV.
This value is composed of almost equal components.
The previous calculations are given only as a guide.
Capacitor parameters usually have large tolerances
and can be susceptible to environmental conditions.
If the SYNC
pin is being used, then the trace
connection between device SYNC
IN
pins should be
short to avoid stray capacitance. If the SYNC
IN
pin is
not being used, it is advisable to place a guard ring
(connected to input ground) around this pin to avoid
any noise pick up.
The output should be taken from the device using
ground and power planes; this ensures minimum
losses.
the
two
conventional
13
shows
the
A good quality low-ESR ceramic capacitor placed as
close as practical across the input reduces reflected
ripple and ensures a smooth startup.
Input power and ground planes have been used,
providing a low-impedance path for the input power.
For the output, the common or 0V has been
connected via a ground plane, while the connections
for the positive and negative voltage outputs are
conducted via wide traces in order to minimize
losses.
A
preferred) placed as close as practical across the
rectifier output terminal and output ground gives the
best ripple and noise performance. See Application
Bulletin
SBVA012,
DC-to-DC
Reduction
, for more information on noise rejection.
good
quality
low-ESR
capacitor
(ceramic
Converter
Noise
The location of the decoupling capacitors in close
proximity to their respective pins ensures low losses
due
to
the
effects
of
improving the ripple performance. This location is of
particular
importance
to
capacitor,
because
this
transient current associated with the fast switching
waveforms of the power drive circuits.
stray
inductance;
thus,
the
capacitor
input
decoupling
supplies
the
10
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