參數(shù)資料
型號： DC979A
廠商： Linear Technology
文件頁數(shù)： 10/32頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2442
軟件下載： QuikEval System
設(shè)計資源： DC979A Design File
DC979A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 8k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2442
已供物品： 板
相關(guān)產(chǎn)品： LTC2442IG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP
LTC2442CG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP
LTC2442IG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP
LTC2442CG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP
LTC2442
18
2442fa
For more information www.linear.com/LTC2442
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface.
The conversion result is shifted out of the device by an
externally generated serial clock (SCK) signal, see Figure
6. CS may be permanently tied to ground, simplifying the
user interface or isolation barrier. The external serial clock
mode is selected by tying EXT LOW.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. Conversely, BUSY (Pin 2) may
be used to monitor the status of the conversion cycle.
EOC or BUSY may be used as an interrupt to an external
controller indicating the conversion result is ready. EOC =
1 (BUSY = 1) while the conversion is in progress and EOC
= 0 (BUSY = 0) once the conversion enters the sleep state.
On the falling edge of EOC/BUSY, the conversion result
is loaded into an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK.
Data is shifted out the SDO pin on each falling edge of
SCK enabling external circuitry to latch data on the rising
edge of SCK. EOC can be latched on the first rising edge
of SCK. On the 32nd falling edge of SCK, SDO and BUSY
go HIGH (EOC = 1) indicating a new conversion has begun.
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
2442 F06
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
MSB
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
BIT 0
LSB
SIG
BIT 29
“0”
BIT 30
EOC
BIT 31
1
0
EN
SGL
0
A0
OSR3 OSR2 OSR1 OSR0 TWOX
ODD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
32
DON'T CARE
VCC
V+
+INA
MUXOUTA
BUSY
SDO
SDI
EXT
SCK
FO
MUXOUTB
+INB
GND
21
6
7
8
9
28
12
13
11
17
18
10
26
25
4, 5, 32
19
27
2
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
24
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
(SIMULTANEOUS 50Hz/60Hz
REJECTION AT 6.9Hz OUTPUT RATE
1F
0.1F
4.5V TO 5.5V
VCC TO 15V
LTC2442
1F
0.1F
CS
–15V TO GND
V–
REF+
REF–
OUTB
–INB
ADCINB
CH0
CH1
CH2
CH3
COM
29
30
31
3
33
1
36
35
OUTA
–INA
ADCINA
3-WIRE
SPI INTERFACE
Figure 6. External Serial Clock, CS = 0 Operation (2-Wire)
applications inForMation
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