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參數(shù)資料
| 型號： | DC579A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 0K |
| 描述： | BOARD DAC LTC2600 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC579A Design File DC579A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™ |
| DAC 的數(shù)量： | 8 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時間： | 10µs |
| DAC 型： | 電壓 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC2600 |
| 相關(guān)產(chǎn)品： | LTC2600IUFD#PBF-ND - IC DAC OCTAL R-R 16BIT 20-QFN LTC2600IUFD#TRPBF-ND - IC DAC OCTAL R-R 16BIT 20-QFN LTC2600CUFD#TRPBF-ND - IC DAC OCTAL R-R 16BIT 20-QFN LTC2600CUFD#PBF-ND - IC DAC OCTAL R-R 16BIT 20-QFN LTC2600IGN#PBF-ND - IC DAC OCTAL R-R 16BIT 16SSOP LTC2600CGN#TRPBF-ND - IC DAC OCTAL R-R 16BIT 16SSOP LTC2600IGN#TRPBF-ND - IC DAC OCTAL R-R 16BIT 16SSOP LTC2600CGN#PBF-ND - IC DAC OCTAL R-R 16BIT 16SSOP LTC2600CGN#TR-ND - IC DAC R-R 16-BIT OCTAL 16-SSOP LTC2600IGN#TR-ND - IC DAC R-R 16-BIT OCTAL 16-SSOP 更多... |
LTC2600/LTC2610/LTC2620
14
2600fe
OPERATION
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than eight outputs are needed. When in power-down, the
buffer ampliers and reference inputs are disabled, and
draw essentially zero current. The DAC outputs are put
into a high impedance state, and the output pins are pas-
sively pulled to ground through individual 90k resistors.
When all eight DACs are powered down, the master bias
generation circuit is also disabled. Input- and DAC-register
contents are not disturbed during power-down.
Any channel or combination of channels can be put into
power-down mode by using command 0100b in combi-
nation with the appropriate DAC address, (n). The 16-bit
data word is ignored. The supply and reference currents
are reduced by approximately 1/8 for each DAC powered
down; the effective resistance at REF (Pin 6) rises accord-
ingly, becoming a high impedance input (typically > 1GΩ)
when all eight DACs are powered down.
Normal operation can be resumed by executing any
command which includes a DAC update, as shown in
Table 1. The selected DAC is powered up as its voltage
output is updated.
There is an initial delay as the DAC powers up before it
begins its usual settling behavior. If less than eight DACs
are in a powered-down state prior to the update command,
the power-up delay is 5μs. If, on the other hand, all eight
DACs are powered down, then the master bias genera-
tion circuit is also disabled and must be restarted. In this
case, the power-up delay is greater: 12μs for VCC = 5V,
30μs for VCC = 3V.
Voltage Outputs
Each of the 8 rail-to-rail ampliers contained in these parts
has guaranteed load regulation when sourcing or sinking
up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
per milliampere of forced load current change is expressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The ampliers’ DC output
impedance is 0.025Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 25Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
25Ω 1mA = 25mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The ampliers are stable driving capacitive loads of up
to 1000pF.
Board Layout
The excellent load regulation and DC crosstalk performance
of these devices is achieved in part by keeping “signal”
and “power” grounds separated internally and by reducing
shared internal resistance to just 0.005Ω.
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