參數(shù)資料
型號(hào)： DC1620A-L
廠商： Linear Technology
文件頁(yè)數(shù)： 18/38頁(yè)
文件大小： 0K
描述： BOARD DEMO 25MSPS LTC2140-14
軟件下載： QuikEval II System
設(shè)計(jì)資源： DC1620A Design Files
DC1620A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： *
相關(guān)產(chǎn)品： DC890B-ND - BOARD USB DATA COLLECTION
25
21421014fa
LTC2142-14/
LTC2141-14/LTC2140-14
APPLICATIONS INFORMATION
Phase Shifting the Output Clock
In full rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
set-up and hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2142-14/LTC2141-14/LTC2140-14 can also phase
shift the CLKOUT+/CLKOUT– signals by serially program-
ming mode control register A2. The output clock can be
shifted by 0°, 45°, 90°, or 135°. To use the phase shift-
ing feature the clock duty cycle stabilizer must be turned
on. Another control register bit can invert the polarity of
CLKOUT+ and CLKOUT–, independently of the phase shift.
The combination of these two features enables phase shifts
of 45° up to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>1.000000V
+0.999878V
+0.999756V
1
0
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1110
+0.000122V
+0.000000V
–0.000122V
–0.000244V
0
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.999878V
–1.000000V
≤–1.000000V
0
1
00 0000 0000 0001
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
CLKOUT+
D0-D13, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
1
CLKPHASE1
MODE CONTROL BITS
0
1
0
1
CLKPHASE0
0
1
0
1
0
1
0
1
21421014 F14
ENC+
Figure 14. Phase Shifting CLKOUT
相關(guān)PDF資料
PDF描述
DC1620A-K BOARD DEMO 40MSPS LTC2141-14
VX-53-1C23 SWITCH LEVER SPDT 5A .187QC
370 T 1 3/4 18V .04 AMP LAMP
DC1620A-J BOARD DEMO 65MSPS LTC2142-14
1850 LAMP T3-1/4 MINI BAYONET BASE
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DC1620A-P 功能描述:BOARD DEMO 65MSPS LTC2142-12 RoHS:是 類別:未定義的類別 >> 其它 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* 其它名稱:MS305720A
DC1620A-Q 功能描述:BOARD DEMO 40MSPS LTC2141-12 RoHS:是 類別:未定義的類別 >> 其它 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* 其它名稱:MS305720A
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