參數(shù)資料
型號(hào)： DC1562A-I
廠商： Linear Technology
文件頁(yè)數(shù)： 8/26頁(yè)
文件大小： 0K
描述： BOARD EVAL LTC6993-3
設(shè)計(jì)資源： DC1562A Design Files
DC1562A Schematic
特色產(chǎn)品： TimerBlox?
標(biāo)準(zhǔn)包裝： 1
系列： TimerBlox®
主要目的： 定時(shí)，單穩(wěn)多諧振蕩器
嵌入式： 否
已用 IC / 零件： LTC6993-3
主要屬性： 下降沿觸發(fā)器，不可再觸發(fā)
次要屬性： 2.25 V ~ 5.5 V 電源
已供物品： 板
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
16
69931234fb
APPLICATIONS INFORMATION
Basic Operation
The simplest and most accurate method to program
the LTC6993 is to use a single resistor, RSET, between
the SET and GND pins. The design procedure is a four
step process. Alternatively, Linear Technology offers the
easy-to-use TimerBlox Designer tool to quickly design
any LTC6993 based circuit. Download the free TimerBlox
Designer software at www.linear.com/timerblox.
Step 1: Select the POL Bit Setting.
The LTC6993 can generate positive or negative output
pulses, depending on the setting of the POL bit. The POL
bit is the DIVCODE MSB, so any DIVCODE ≥ 8 has POL = 1
and produces active-low pulses.
Step 2: Select LTC6993 Version.
Two input-related choices dictate the proper LTC6993 for
a given application:
Is TRIG a rising or falling-edge input?
Should retriggering be allowed?
Use Table 2 to select a particular variety of LTC6993.
Step 3: Select the NDIV Frequency Divider Value.
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the NDIV
value. For a given output pulse width (tOUT), NDIV should
be selected to be within the following range:
tOUT
16s
≤NDIV ≤
tOUT
1s
(1)
To minimize supply current, choose the lowest NDIV value.
However,insomecasesahighervalueforNDIVwillprovide
better accuracy (see Electrical Characteristics).
Table 1 can also be used to select the appropriate NDIV
values for the desired tOUT.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Step 4: Calculate and Select RSET.
The final step is to calculate the correct value for RSET
using the following equation:
RSET =
50k
1s
tOUT
NDIV
(2)
Select the standard resistor value closest to the calculated
value.
Example: Design a one-shot circuit that satisfies the fol-
lowing requirements:
tOUT = 100s
Negative Output Pulse
Rising-Edge Trigger Input
Retriggerable Input
Minimum power consumption
Step 1: Select the POL Bit Setting.
For inverted (negative) output pulse, choose POL = 1.
Step 2: Select the LTC6993 Version.
A rising-edge retriggerable input requires the LTC6993-2.
Step 3: Select the NDIV Frequency Divider Value.
Choose an NDIV value that meets the requirements of
Equation (1), using tOUT = 100s:
6.25 ≤ NDIV ≤ 100
Potential settings for NDIV include 8 and 64. NDIV = 8 is
the best choice, as it minimizes supply current by us-
ing a large RSET resistor. POL = 1 and NDIV = 8 requires
DIVCODE = 14. Using Table 1, choose R1 = 102k and
R2 = 976k values to program DIVCODE = 14.
Step 4: Select RSET.
Calculate the correct value for RSET using Equation (2):
RSET =
50k
1s
100s
8
= 625k
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DC1562A-J 功能描述:BOARD EVAL LTC6993-4 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱(chēng):82EBV2081
DC1562A-K 功能描述:BOARD EVAL LTC6994-1 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱(chēng):82EBV2081
DC1562A-L 功能描述:BOARD EVAL LTC6994-2 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱(chēng):82EBV2081
DC1562B-B 制造商:Linear Technology 功能描述:LTC6991 DEMO BOARD 1Hz (1s) Fixed Frequenc
DC1562B-C 制造商:Linear Technology 功能描述:LTC6992-1 DEMO BOARD 10kHz, 0 100% Duty Cycle
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