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參數(shù)資料
| 型號： | DC1546A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DAC LTC2754-16 |
| 軟件下載： | QuikEval System |
| 設計資源： | DC1546A Design Files DC1546A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™, SoftSpan™ |
| DAC 的數(shù)量： | 4 |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 設置時間： | 2µs |
| DAC 型： | 電流 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC2754-16 |
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LTC2754
16
2754f
OPERATION
System Offset and Reference Adjustments
The LTC2754 has individual offset- and gain- adjust pins
(VOSADJX and GEADJX, respectively) for each of its four
DACs.
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2754, which is so low as to be
dominated by external output amplier errors even when
using the most precise op amps.
The offset adjust pins VOSADJX can be used to null
unipolar offset or bipolar zero error. The offset-voltage
delta is inverted and attenuated such that a 5V control
voltage applied to VOSADJX produces ΔVOS = –512 LSB
(LTC2754-16) in any output range (assumes a 5V refer-
ence voltage at RINX).
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
ΔVOS = –(1/128)VOSADJX [0V to 5V, ±2.5V spans]
ΔVOS = –(1/64)VOSADJX [0V to 10V, ±5V, –2.5V to 7.5V
spans]
ΔVOS = –(1/32)VOSADJX [±10V span]
The gain error adjust pins GEADJX can be used to null
gain error or to compensate for reference errors. Nominal
adjustment range is ±512 LSB (LTC2754-16) for a volt-
age input range of ±VRINX (i.e., ±5V for a 5V reference
input). The gain-error delta is non-inverting for positive
reference voltages.
Note that these pins compensate the gain by altering the
inverted reference voltage VREFX.Involtageterms,theVREFX
delta is inverted and attenuated by a factor of 128.
ΔVREFX = –(1/128)GEADJX
The nominal input range of these pins is ±5V; other volt-
ages of up to ±15V may be used if needed. However, do
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the performance of which the part is capable.
The VOSADJX pins have an input impedance of 1.28MΩ.
These pins should be driven with a Thevenin-equivalent
impedance of 10k or less to preserve the settling
performance of the LTC2754. They should be shorted to
GND if not used.
The GEADJX pins have an input impedance of 2.56MΩ, and
are intended for use with xed reference voltages only.
They should be shorted to GND if not used. If the reference
inverting resistors are not used for that channel, then
GEADJX, RCOMX and RINX should all be shorted to REFX.
Power-On Reset and Clear
When power is rst applied to the LTC2754, all DACs
power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
initialize to zero volts.
If the part is congured for manual span operation, all four
DACs will be set into the pin-strapped range at the rst
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to 0 and the DAC outputs are
all reset to zero volts. The Input buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed DACs to their respective
previous states.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a ag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply VDD dips below
approximately 2V; and stays asserted until any valid Update
command is executed.
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