參數(shù)資料
型號(hào)： DC1383A-A
廠商： Linear Technology
文件頁(yè)數(shù)： 19/20頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2451
軟件下載： QuikEval System
設(shè)計(jì)資源： DC1383A Design File
DC1383A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 60
數(shù)據(jù)接口： I²C，串行
輸入范圍： ±VREF
已用 IC / 零件： LTC2451
已供物品： 板
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LTC2451
8
2451fg
APPLICATIONS INFORMATION
CONVERTER OPERATION
Converter Operation Cycle
The LTC2451 is a low power, delta-sigma analog-to-
digital converter with an I2C interface. Its operation, as
showninFigure1,iscomposedofthreesuccessivestates:
conversion, sleep, and data input/output.
Initially, at power-up, the LTC2451 is set to its default 60Hz
mode and performs a conversion. Once the conversion is
complete, the device enters the sleep state. While in the
sleep state, power consumption is reduced by several
orders of magnitude. The part remains in the sleep state
as long it is not addressed for a read or write operation.
The conversion result is held indefinitely in a static shift
register while the part is in the sleep state.
The device will not acknowledge an external request dur-
ing the conversion state. After a conversion is finished,
the device is ready to accept a read/write request. The
LTC2451’s address is hard wired at 0010100. Once the
LTC2451 is addressed for a read operation, the device
begins outputting the conversion result under the control
of the serial clock (SCL). There is no latency in the conver-
sion result. The data output is 16 bits long and outputs
from MSB to LSB. Data is updated on the falling edges of
SCL, allowing the user to reliably latch data on the rising
edge of SCL. In write operation, the device accepts one
configuration byte and the data is shifted in on the rising
edges of SCL. A new conversion is initiated by a STOP
condition following a valid read or write operation, or by
the conclusion of a complete read cycle (all 16 bits read
out of the device).
Power-Up Sequence
When the power supply voltage, VCC, applied to the con-
verter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When VCC rises above this threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2451 starts
a conversion cycle and follows the succession of states
described in Figure 1. The first conversion result follow-
ing POR is accurate within the specifications of the device
if the power supply voltage, VCC, is restored within the
operating range (2.7V to 5.5V) before the end of the POR
time interval.
Ease of Use
The LTC2451 data output has no latency, filter settling
delay, or redundant results associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog input voltages requires no special actions.
Inthe30Hzmode,theLTC2451performsoffsetcalibrations
during every conversion. This calibration is transparent to
the user and has no effect upon the cyclic operation previ-
ously described. The advantage of continuous calibration
is stability of the ADC performance with respect to time
and temperature.
TheLTC2451includesaproprietaryinputsamplingscheme
that reduces the average input current by several orders
of magnitude when compared to traditional delta-sigma
architectures.Thisallowsexternalfilternetworkstointerface
directly to the LTC2451. Since the average input sampling
current is 50nA, an external RC lowpass filter using a 1kΩ
and 0.1F results in less than 1LSB additional error.
Figure 1. State Diagram
READ/WRITE
ACKNOWLEDGE
DATA INPUT/OUTPUT
YES
2451 F01
STOP
OR READ
16 BITS
SLEEP
CONVERSION
POWER-ON RESET
NO
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