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參數(shù)資料
| 型號： | DC1082A-F |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC2355-14 |
| 軟件下載： | QuikEval II System |
| 設計資源： | DC1082A Design File DC1082A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | 0 ~ 2.5 V |
| 已用 IC / 零件： | LTC2355-14 |
| 已供物品： | 板 |
| 相關產(chǎn)品： | LTC2355IMSE-14#TRPBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355CMSE-14#TRPBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355CMSE-12#TRPBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2355IMSE-12#TRPBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2355IMSE-14#PBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355IMSE-12#PBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2355CMSE-14#PBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2355CMSE-12#PBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP |
LTC2355-12/LTC2355-14
2355fa
applications inFormation
The Typical Application Figure on page 16 shows a cir-
cuit for level-shifting and squaring the output from an
RF signal generator or other low-jitter source. A single
D-type flip flop is used to generate the CONV signal to
the LTC2355-12/LTC2355-14. Re-timing the master clock
signal eliminates clock jitter introduced by the controlling
device(DSP,FPGA,etc.)Boththeinverterandflipflopmust
be treated as analog components and should be powered
from a clean analog supply.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK starts clocking
out the 12/14 data bits with the MSB sent first. A simple
approach is to generate SCK to drive the LTC2355-12/
LTC2355-14 first and then buffer this signal with the
appropriate number of inverters to drive the serial clock
input of the processor serial port. Use the falling edge of
the clock to latch data from the Serial Data Output (SDO)
into your processor serial port. The 14-bit serial data will
be received right justified, in a 16-bit word with 16 or
more clocks per frame sync. It is good practice to drive
the LTC2355-12/LTC2355-14 SCK input first to avoid digi-
tal noise interference during the internal bit comparison
decision by the internal high speed comparator. Unlike the
CONV input, the SCK input is not sensitive to jitter because
the input signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out 12/14 bits in the output data stream beginning at the
third rising edge of SCK after the rising edge of CONV.
SDO is always in high impedance mode when it is not
sending out data bits. Please note the delay specification
from SCK to a valid SDO. SDO is always guaranteed to
be valid by the next rising edge of SCK. The 16-bit output
data stream is compatible with the 16-bit or 32-bit serial
port of most processors.
Loading on the SDO line must be minimized. SDO can
directly drive most fast CMOS logic inputs directly. How-
ever, the general purpose I/O pins on many programmable
logic devices (FPGAs, CPLDs) and DSPs have excessive
capacitance. In these cases, a 100Ω resistor in series
with SDO can isolate the input capacitance of the receiv-
ing device. If the receiving device has more than 10pF
of input capacitance or is located far from the LTC2355-
12/LTC2355-14, an NC7SVU04P5X inverter can be used
to provide more drive.
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