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參數(shù)資料
| 型號(hào)： | DC1082A-E |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 18/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD SAR ADC LTC2356-14 |
| 軟件下載： | QuikEval II System |
| 設(shè)計(jì)資源： | DC1082A Design File DC1082A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 3M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 輸入范圍： | ±1.25 V |
| 已用 IC / 零件： | LTC2356-14 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2356CMSE-12#TRPBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2356CMSE-14#TRPBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2356IMSE-14#TRPBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2356IMSE-12#TRPBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2356CMSE-14#PBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2356IMSE-14#PBF-ND - IC ADC 14BIT 3.5MSPS 10-MSOP LTC2356IMSE-12#PBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP LTC2356CMSE-12#PBF-ND - IC ADC 12BIT 3.5MSPS 10-MSOP |
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LTC2356-12/LTC2356-14
9
2356fb
2356 BD
–
+
1
2
7
3
4
S & H
GND
EXPOSED PAD
LTC2356-14
VREF
10F
AIN–
AIN+
14-BIT ADC
3.3V
10F
14
14-BIT
LA
TCH
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
2.5V
REFERENCE
TIMING
LOGIC
VDD
SDO
CONV
SCK
5
6
11
PIN FUNCTIONS
A(Pin 1): Noninverting Analog Input. AIN+ operates
fully differentially with respect to AIN– with a –1.25V to
1.25V differential swing with respect to AIN– and a 0V to
VDD common mode swing.
AIN– (Pin 2): Inverting Analog Input. AIN– operates fully
differentially with respect to AIN+ with a 1.25V to –1.25V
differential swing with respect to AIN+ and a 0V to VDD
common mode swing.
VREF (Pin 3): 2.5V Internal Reference. Bypass to GND
and to a solid analog ground plane with a 10F ceramic
capacitor(or10Ftantaluminparallelwith0.1Fceramic).
Can be overdriven by an external reference between 2.55V
and VDD.
GND (Pins 4, 5, 6, 11): Ground and Exposed Pad. These
ground pins and the exposed pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
flow through these pins.
VDD (Pin 7): 3.3V Positive Supply. This single power pin
supplies 3.3V to the entire device. Bypass to GND and to
a solid analog ground plane with a 10F ceramic capacitor
(or 10F tantalum in parallel with 0.1F ceramic). Keep in
mind that internal analog currents and digital output signal
currents flow through this pin. Care should be taken to
place the 0.1F bypass capacitor as close to Pins 6 and
7 as possible.
SDO (Pin 8): Three-State Serial Data Output. Each set
of output data words represents the difference between
AIN+ and AIN– analog inputs at the start of the previous
conversion. The output format is 2’s complement.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. Responds to TTL (≤3.3V) and 3.3V CMOS levels.
One or more pulses wake from sleep.
CONV(Pin10):ConvertStart.Holdstheanaloginputsignal
and starts the conversion on the rising edge. Responds
to TTL (≤3.3V) and 3.3V CMOS levels. Two CONV pulses
with SCK in fixed high or fixed low state start Nap mode.
Four or more CONV pulses with SCK in fixed high or fixed
low state start Sleep mode.
BLOCK DIAGRAM
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