參數(shù)資料
型號(hào)： DC1067A-A
廠商： Linear Technology
文件頁(yè)數(shù)： 3/20頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2450
軟件下載： QuikEval System
設(shè)計(jì)資源： DC1067A Design File
DC1067A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 30
數(shù)據(jù)接口： 串行，SPI?
已用 IC / 零件： LTC2450
已供物品： 板
相關(guān)產(chǎn)品： LTC2450IDC#TRPBF-ND - IC ADC 16BIT DELTA SIG 6-DFN
LTC2450IDC-1#TRPBF-ND - IC ADC 16BIT DELTA SIG 6-DFN
LTC2450IDC-1#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 6-DFN
LTC2450IDC#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 6-DFN
LTC2450CDC-1#TRPBF-ND - IC ADC 16BIT DELTA SIG 6-DFN
LTC2450CDC-1#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 6-DFN
LTC2450CDC#TRPBF-ND - IC ADC 16BIT DELTA SIG 6-DFN
LTC2450CDC#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 6-DFN
LTC2450
11
2450fb
Examples of Aborting Cycle using CS
For some applications the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2450 is in the
data output state, a CS rising edge clears the remaining data
bits from memory, aborts the output cycle and triggers a
new conversion. Figure 9 shows an example of aborting
an I/O with idle-high (CPOL = 1) and Figure 10 shows an
example of aborting an I/O with idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 11. If SCK is maintained at a LOW
logic level, after the end of a conversion cycle, a new
conversion operation can be triggered by pulling CS low
and then high. When CS is pulled low (CS = LOW), SDO
will output the most signicant bit (D15) of the result of
the just completed conversion. While a low logic level is
maintained at SCK pin and CS is subsequently pulled high
(CS = HIGH) the remaining 15 bits of the result (D14:D0)
are discarded and a new conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal tran-
sitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively inuence
the conversion accuracy.
APPLICATIONS INFORMATION
D15
D14
D13
D12
D2
D1
D0
SD0
clk1
clk2
clk3
clk4
clk15
clk16
SCK
CONVERT
SLEEP
LOW ICC
DATA OUTPUT
2450 F08
CS
Figure 8. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
D15
D14
D13
D12
D2
D1
D0
clk1
clk2
clk3
clk4 clk14
clk15
clk16
SCK
SD0
CONVERT
SLEEP
LOW ICC
DATA OUTPUT
2450 F07
CS
Figure 7. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
相關(guān)PDF資料
PDF描述
0210390933 CABLE JUMPER 1MM .178M 23POS
PCMC135T-2R2MF COIL 2.2 UH POWER CHOKE 20% SMD
AT-S-26-6/6/B-25-OE-R MOD CORD SGL-ENDED 6-6 BLACK 25'
MIC2005-0.5LYM5 TR IC DISTRIBUTION SW 0.5A SOT23-5
GSM10DSEI CONN EDGECARD 20POS .156 EYELET
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DC1067A-B 功能描述:BOARD DELTA SIGMA ADC LTC2450-1 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:QuikEval™ 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
DC106R 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
DC107 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
DC1073A 制造商:Linear Technology 功能描述:LT3845EFE DEMO BOARD
DC1074A 功能描述:BOARD DAC LTC2630-12 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:QuikEval™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*