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參數(shù)資料
| 型號： | DAC8512GBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | % V, Serial Input Complete 12-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 16 us SETTLING TIME, 12-BIT DAC, UUC8 |
| 封裝： | DIE-8 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 757K |
| 代理商： | DAC8512GBC |
DAC8512
–18–
REV. A
DAC8512–M68HC11 Interface Program Source Code
*
PORTC
*
DDRC
PORTD
*
DDRD
SPCR
*
SPSR
*
SPDR
*
EQU
$1003
Port C control register
“0,0,0,0;0,0,CLR/,CS/”
Port C data direction
Port D data register
“0,0,LD/,SCLK;SDI,0,0,0
Port D data direction
SPI control register
“SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPRl,SPR0”
SPI status register
“SPIF,WCOL,0,MODF;0,0,0,0”
SPI data register; Read-Buffer; Write-Shifter
EQU
EQU
$1007
$1008
EQU
EQU
$1009
$1028
EQU
$1029
EQU
$102A
* SDI RAM variables:
*
*
*
*
SDI1
SDI2
*
SDI1 is encoded from 0 (Hex) to F (Hex)
SDI2 is encoded from 00 (Hex) to FF (Hex)
DAC requires two 8-bit loads; upper 4 bits of SDI1
are ignored.
EQU
EQU
$00
$01
SDI packed byte 1 “0,0,0,0;MSB,DB10,DB9,DB8”
SDI packed byte 2 “DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0”
ORG
LDS
$C000
#$CFFF
Start of user’s RAM in EVB
Top of C page RAM
INIT
*
LDAA
#$03
0,0,0,0;0,0,1,1
CLR/-Hi, CS/-Hi
Initialize Port C Outputs
0,0,0,0;0,0,1,1
CLR/ and CS/ are now enabled as outputs
*
STAA
LDAA
STAA
PORTC
#$03
DDRC
*
LDAA
#$30
0,0,1,1;0,0,0,0
LDI-Hi,SCLK-Hi,SDI-Lo
Initialize Port D Outputs
0,0,1,1;1,0,0,0
LD/,SCLK, and SDI are now enabled as outputs
*
STAA
LDAA
STAA
PORTD
#$38
DDRD
*
LDAA
STAA
#$5F
SPCR
SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32
*
BSR
JMP
UPDATE
$E000
Xfer 2 8-bit words to DAC8512
Restart BUFFALO
*
UPDATE
PSHX
PSHY
PSHA
Save registers X, Y, and A
*
LDAA
STAA
#$0A
SDI1
0,0,0,0;1,0,1,0
SDI1 is set to 0A (Hex)
*
LDAA
STAA
#$AA
SDI2
1,0,1,0;1,0,1,0
SDI2 is set to AA (Hex)
*
LDX
LDY
#SDI1
#$1000
Stack pointer at 1st byte to send via SDI
Stack pointer at on-chip registers
*
BCLR
PORTC,Y
$02 Assert CLR/
$02 De-assert CLR/
BSET
PORTC,Y
*
BCLR
PORTC,Y
$01 Assert CS/
*
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