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參數(shù)資料
| 型號： | DAC8512FSZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SRL LP 5V 8SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 16µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 62.5k |
DAC8512
–13–
REV. A
Opto-Isolated Interfaces for Process Control Environments
In many process control type applications, it is necessary to pro-
vide an isolation barrier between the controller and the unit be-
ing controlled. Opto-isolators can provide isolation in excess of
3 kV. The serial loading structure of the DAC8512 makes it
ideal for opto-isolated interfaces as the number of interface lines
is kept to a minimum.
Illustrated in Figure 34 is an opto-isolated interface using the
DAC8512. In this circuit, the CS line is always LOW to enable
the DAC, and the 10 k
/1 F combination connected to the
DAC’s CLR pin sets a turn-on time constant of 10 ms to reset
the DAC upon application of power. Three opto-couplers are
then used for the SDI, SCLK, and LD lines.
Often times reducing the number of interface lines to two lines
is required in many control environments. The circuit illustrated
in Figure 35 shows how to convert a two-line interface into the
three control lines required to control the DAC8512 without us-
ing one shots. This technique uses a counter to keep track of the
clock cycles and, when all the data has been input to the DAC,
the external logic generates the LD pulse.
0.1
F
+5V
5
6
8
DAC8512
1
CS
3
4
7
2
0.1
F
10k
+5V
VOUT
+5V
10k
SCLK
10k
SDI
10k
LD
SCLK
SDI
+5V
REG
+5V
POWER
HIGH VOLTAGE
ISOLATION
Figure 34. An Opto-Isolated DAC Interface
+5V
10k
10k
SCLK
SDI
+5V
REG
+5V
POWER
HIGH VOLTAGE
ISOLATION
74HC161
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLR
CLK
A
B
C
D
ENP
GND
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
+5V
10k
NC
0.1
F
+5V
10k
X
1
2
3
Y
4
5
6
1/4 74HCOO
V
DD
0.1
F
3
5
8
DAC8512
1
+5V
4
LD
SCLK
SDI
7
6
CLR
GND
V
OUT
CS
2
+5V
10k
1
F
Figure 35. A Two-Wire, Opto-lsolated DAC Interface
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