WAFER TEST LIMITS at VDD = +5 V; V
參數(shù)資料
型號(hào): DAC8408FSZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 12/16頁(yè)
文件大?。?/td> 0K
描述: IC DAC 8BIT QUAD W/MEMORY 28SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 27
設(shè)置時(shí)間: 190ns
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
輸出數(shù)目和類型: 4 電流,單極;4 電流,雙極
采樣率(每秒): 5.26M
DAC8408
–5–
REV. A
WAFER TEST LIMITS at VDD = +5 V; VREF = 10 V; VOUTA, B, C, D = 0 V; TA = +25 C, unless otherwise noted. Specifications apply for
DAC A, B, C, & D.
DAC8408G
Parameter
Symbol
Conditions
Limits
Units
STATIC ACCURACY
Resolution
N
8
Bits min
Nonlinearity
1
INL
±1/2
LSB max
Differential Nonlinearity
DNL
±1
LSB max
Gain Error
GFSE
Using Internal RFB
±1
LSB max
Power Supply Rejection
PSR
Using Internal RFB
0.001
%FSR/% max
(
V
DD =
±10%)2
IOUT 1A, B, C, D Leakage Current
ILKG
All Digital Inputs = 0 V
±30
nA max
VREF = +10 V
REFERENCE INPUT
Reference Input
RIN
6/14
k
min/max
Resistance
3
Input Resistance Match
RIN
±1
% max
DIGITAL INPUTS
Digital Input Low
VIL
0.8
V max
Digital Input High
VIH
2.4
V min
Input Current
4
IIN
±1.0
A max
DATA BUS OUTPUTS
Digital Output Low
VOL
1.6 mA Sink
0.4
V max
Digital Output High
VOH
400
A Source
4
V min
Output Leakage Current
ILKG
±1.0
A max
POWER SUPPLY
Supply Current
5
IDD
50
A max
Supply Current6
IDD
1.0
mA max
NOTES
1This is an endpoint linearity specification.
2FSR is Full Scale Range = V
REF –1 LSB.
3Input Resistance Temperature Coefficient approximately equals +300 ppm/
°C.
4Logic inputs are MOS gates.Typical input current at +25
°C is less than 10 nA.
5All Digital Inputs are either “0” or V
DD.
6All Digital Inputs are either V
IH or VIL.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
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