參數(shù)資料
型號: DAC8222FPZ
廠商: Analog Devices Inc
文件頁數(shù): 2/15頁
文件大?。?/td> 0K
描述: IC DAC 12BIT DUAL W/BUFF 24DIP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 15
設(shè)置時間: 1µs
位數(shù): 12
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 24-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 24-PDIP
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 1M
DAC8222
–10–
REV. C
Figure 24. Unipolar Configuration (Two-Quadrant Multiplication)
APPLICATIONS INFORMATION
UNIPOLAR OPERATION
Figure 24 shows a simple unipolar (2-quadrant multiplication)
circuit using the DAC8222 and OP270 dual op amp (use two
OP42s for higher speeds), and Table II the corresponding code
table. Resistors R1, R2, and R3, R4 are used only if full-scale
gain adjustments are required. Low temperature coefficient
(approximately 50 ppm/
°C) resistors or trimmers should be
used. Maximum full-scale error without these resistors for the
top grade device and VREF =
±10 V is 0.024% and 0.097% for
the low grade. C1 and C2 provide phase compensation to help
reduce overshoot and ringing when high speed op amps are used.
Full-scale adjustment is accomplished by loading the digital
inputs with all 1s and adjusting R1 (or R3) so that
VOUT = VREF
×
4095
4096
Full-scale can also be adjusted by varying VREF voltage, thus
eliminating R1, R2, R3 and R4. Zero adjustment is performed
by setting the DAC’s digital inputs to all 0s and adjusting the op
amp’s offset adjust so that VOUT = 0 V. To maintain monotonic-
ity and minimize gain and linearity errors, it is recommended
that the op amp offset voltage be adjusted to less than 10% of
1 LSB (244
V) over the operating temperature range of interest.
Table II. Unipolar Binary Code Table (Refer to Figure 24)
Binary Number in
DAC Register
Analog Output, VOUT
MSB
LSB
(DAC A or DAC B)
1111 1111 1111
–VREF
4095
4096
1000 0000 0000
–VREF
2048
4096
= –1/2 VREF
0000 0000 0001
–VREF
1
4096
0000 0000 0000
0 V
NOTE
1 LSB = (2
–12) (V
REF) =
1
4096
(VREF)
BIPOLAR OPERATION
The bipolar (offset binary) four-quadrant operation configura-
tion using the DAC8222 is shown in Figure 25 and the corre-
sponding code in Table III. The circuit makes use of the OP470
a quad op amp (use four OP42s for higher speeds).
Resistors R1, R2, R3, and R4 may be omitted and full-scale
output voltage may be adjusted by varying VREF or the value
of R5 and R8. If resistors R1, R2, R3, and R4 are omitted,
* RESISTORS R1 THROUGH R4 ARE ONLY NECESSARY TO TRIM FOR
ABSOLUTE ACCURACY BETTER THAN
0.01%, SEE TEXT FOR
COMPLETE DETAILS.
** REGISTERS AND CONTROL CIRCUITRY OMITTED FOR SIMPLICITY.
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