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參數(shù)資料
| 型號： | DAC8043FSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT MULT SRL INP 8SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 47 |
| 設(shè)置時間： | 250ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 500µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | 366k |
DAC8043
Rev. E | Page 14 of 16
INTERFACING TO THE MC6800
As shown in Figure 20, the DAC8043 may be interfaced to the
MC6800 by successively executing memory write instructions
while manipulating the data between writes, so that each write
presents the next bit.
In this example, the most significant bits are found in the 0000
and 0001 memory locations. The four MSBs are found in the
lower half of 0000 and the eight LSBs in 0001. The data is taken
from the DB7 line.
The serial data loading is triggered by the CLK pulse, which
is asserted by a decoded memory write to the 2000 memory
location, R/W, and Φ2. A write to address location 4000
transfers data from the input register to the DAC register.
00271-
020
74LS138
ADDRESS
DECODER
A0
A15
DB0
DB7
E1
E3
E2
A2
SRI
CLK
LD
DAC8043*
16-BIT DATA BUS
R/W
Φ2
8-BIT DATA BUS
MC6800
*ANALOG CIRCUITRY OMITTED
FOR SIMPLICITY.
Figure 20. DAC8043 to MC6800 Interface
DAC8043 INTERFACE TO THE 8085
The interface of the DAC8043 to the 8085 microprocessor
is shown in Figure 21. Note that the SOD line of the micro-
processor is used to present data serially to the DAC.
Data is clocked into the DAC8043 by executing memory write
instructions. The clock input is generated by decoding Address
8000 and WR. Data is loaded into the DAC register with a
memory write instruction to Address A000.
Serial data supplied to the DAC8043 must be present in
the right-justified format in Register H and Register L of the
microprocessor.
00271-
021
A0
A15
AD0
AD7
(8)
ALE
SOD
SRI
*ANALOG CIRCUITRY OMITTED FOR
SIMPLICITY.
CLK
LD
DAC8043*
ADDRESS BUS (16)
DATA
8085
8212
WR
74LS138
ADDRESS
DECODER
A0
E1
E3
5V
E2
A2
Figure 21. DAC8043 to 8085 Interface
DAC8043 TO THE 68000 INTERFACE
The interface of the DAC8043 to the 68000 microprocessor is
shown in Figure 22. Serial data to the DAC is taken from one
of the microprocessor’s data bus lines.
00271-
022
A1
A23
AS
VMA
VPA
UDS
DB0
DB15
SRI
CLK
LD
DAC8043*
ADDRESS BUS
DATA BUS
1/4 74HC125
68000
MICRO-
PROCESSOR
*ANALOG CIRCUITRY OMITTED FOR SIMPLICITY.
ADDRESS
DECODE
CS
+
Figure 22. DAC8043 to 68000 Microprocessor Interface
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