參數(shù)資料
型號(hào): DAC7800LU
廠商: TEXAS INSTRUMENTS INC
元件分類: DAC
英文描述: SERIAL INPUT LOADING, 0.4 us SETTLING TIME, 12-BIT DAC, PDSO16
封裝: GREEN, PLASTIC, SOIC-16
文件頁數(shù): 20/23頁
文件大?。?/td> 687K
代理商: DAC7800LU
DAC7800, 7801, 7802
6
SBAS005A
www.ti.com
BLOCK DIAGRAM
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AGND
I
R
V
CS A
(LSB) DB0
DB1
DB2
DB3
DB4
DB5
DGND
I
R
V
CS B
WR
DB11 (MSB)
DB10
DB9
DB8
DB7
DB6
OUT A
FB A
REF A
FB B
REF B
DD
OUT B
DAC7802
TIMING CHARACTERISTICS
At VDD = +5V, and TA = –40oC to +85oC.
PARAMETER
MINIMUM
t1 - Data Setup Time
20ns
t2 - Data Hold Time
15ns
t3 - Chip Select to Write Setup Time
30ns
t4 - Chip Select to Write Hold Time
0ns
t5 - Write Pulse Width
30ns
LOGIC TRUTH TABLE
CSA
CSB
WR
FUNCTION
X
1
No Data Transfer
1
X
No Data Transfer
0
A Rising Edge on CSA or CSB Loads
Data to the Respective DAC
01
DAC A Register Loaded from Data Bus
10
DAC B Register Loaded from Data Bus
00
DAC A and DAC B Registers Loaded
from Data Bus
X = Don’t care.
means rising edge triggered.
PIN CONFIGURATION
DAC7802
DATA
5V
0V
5V
CSA, CSB
WR
t
2
t
1
t
3
t
4
t
5
NOTES: (1) All input signal rise and fall times are measured from 10%
to 90% of +5V. t
R = tR = 5ns. (2) Timing measurement reference level
is
V
IH + VIL
2
.
CK
DAC B
DAC A
12
DGND
18
CS A
5
CS B
20
WR
19
21
V
DD
DAC7802
6
2
I
3
R
OUT A
FB A
23
R
24
I
1
AGND
FB B
OUT B
DAC A Register
CK
DAC B Register
DB11–DB0
4
22
V
REF A
REF B
Top View
DIP
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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