- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376560 > DAC7552IRGT (Texas Instruments, Inc.) 12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER PDF資料下載
參數(shù)資料
| 型號： | DAC7552IRGT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 12-BIT, DUAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 12位雙，超低毛刺，電壓輸出數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/22頁 |
| 文件大?。?/td> | 862K |
| 代理商： | DAC7552IRGT |
www.ti.com
Power Down
Asynchronous Clear
IOVDD and Level Shifters
The DAC7552 can be used with different logic famil-
ies that require a wide range of supply voltages (from
1.8 V to 5.5 V). To enable this useful feature, the
IOVDD pin must be connected to the logic supply
voltage of the system. All DAC7552 digital input and
output pins are equipped with level-shifter circuits.
Level shifters at the input pins ensure that external
logic high voltages are translated to the internal logic
high voltage, with no additional power dissipation.
Similarly, the level shifter for the SDO pin translates
the internal logic high voltage (AVDD) to the external
logic high level (IOVDD). For single-supply operation,
the IOVDD pin can be tied to the AVDD pin.
Daisy-Chain Operation
SERIAL INTERFACE
The DAC7552 is controlled over a versatile 3-wire
serial interface, which operates at clock rates up to
50 MHz and is compatible with SPI, QSPI, Microwire,
and DSP interface standards.
16-Bit Word and Input Shift Register
DAC7552
SLAS442B–JANUARY 2005–REVISED JUNE 2005
register, DAC register, or both are updated with shift
register input data. Bit 13 (DB13) determines whether
the data is for DAC A, DAC B, or both DACs. Bit 12
(DB12)
determines
either
power-down mode (see
Table 2
). All channels are
updated when bits 15 and 14 (DB15 and DB14) are
high.
The DAC7552 has a flexible power-down capability
as described in
Table 2
. Individual channels could be
powered down separately or all channels could be
powered down simultaneously. During a power-down
condition, the user has flexibility to select the output
impedance of each channel. During power-down
operation, each channel can have either 1-k
,
100-k
, or Hi-Z output impedance to ground.
normal
mode
or
The SYNC input is a level-triggered input that acts as
a frame synchronization signal and chip enable. Data
can only be transferred into the device while SYNC is
low. To start the serial data transfer, SYNC should be
taken low, observing the minimum SYNC to SCLK
falling edge setup time, t
4
. After SYNC goes low,
serial data is shifted into the device's input shift
register on the falling edges of SCLK for 16 clock
pulses.
The DAC7552 output is asynchronously set to
zero-scale voltage immediately after the CLR pin is
brought low. The CLR signal resets all internal
registers and therefore behaves like the Power-On
Reset. The DAC7552 updates at the first rising edge
of the SYNC signal that occurs after the CLR pin is
brought back to high.
When DCEN is low, SDO pin is brought to a Hi-Z
state. The first 16 data bits that follow the falling edge
of SYNC are stored in the shift register. The rising
edge of SYNC that follows the 16
th
data bit updates
the DAC(s). If SYNC is brought high before the 16
th
data bit, no action occurs.
When DCEN is high, data can continuously be shifted
into the shift register, enabling the daisy-chain oper-
ation. SDO pin becomes active and outputs SDIN
data with 16 clock cycle delay. A rising edge of SYNC
loads the shift register data into the DAC(s). The
loaded data consists of the last 16 data bits received
into the shift register before the rising edge of SYNC.
If daisy-chain operation is not needed, DCEN should
permanently be tied to a logic low voltage.
When DCEN pin is brought high, daisy chaining is
enabled. Serial Data Output (SDO) pin is provided to
daisy-chain multiple DAC7552 devices in a system.
As long as SYNC is high or DCEN is low, the SDO
pin is in a high-impedance state. When SYNC is
brought low the output of the internal shift register is
tied to the SDO pin. As long as SYNC is low and
DCEN is high, SDO duplicates SDIN signal with a
16-cycle delay. To support multiple devices in a daisy
chain, SCLK and SYNC signals are shared across all
devices, and SDO of one DAC7552 should be tied to
the SDIN of the next DAC7552. For
n
devices in such
a daisy chain, 16
n
SCLK cycles are required to shift
the entire input data stream. After 16
n
SCLK falling
edges are received, following a falling SYNC, the
data stream becomes complete and SYNC can be
brought high to update
n
devices simultaneously.
SDO operation is specified at a maximum SCLK
speed of 10 MHz.
In daisy-chain mode (DCEN = 1), the DAC7552
requires a falling SCLK edge after the rising SYNC, in
order to initialize the serial interface for the next
update.
The input shift register is 16 bits wide. DAC data is
loaded into the device as a 16-bit word under the
control of a serial clock input, SCLK, as shown in the
Figure 1
timing diagram. The 16-bit word, illustrated
in
Table 1
, consists of four control bits followed by 12
bits of DAC data. The data format is straight binary
with all zeroes corresponding to 0-V output and all
ones corresponding to full-scale output (V
REF
– 1
LSB). Data is loaded MSB first (bit 15) where the first
two bits (DB15 and DB14) determine if the input
16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DAC757IDGSR | QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER |
| DAC7611 | Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????) |
| DAC7611P | Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????) |
| DAC7611PB | Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????) |
| DAC7611U | Single Supply RS232C Line Driver/Receiver(?????μ?o?RS232C ?o?????????¨???2???2??????) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC7552IRGTR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Dual UltrLo Glitch Vltg Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7552IRGTRG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Dual UltrLo Glitch Vltg Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7552IRGTT | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Dual UltrLo Glitch Vltg Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC7552IRGTT | 制造商:Texas Instruments 功能描述:IC DAC 12BIT DUAL W/SPI 16-VQFN |
| DAC7552IRGTTG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 12-Bit Dual UltrLo Glitch Vltg Output RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。