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參數(shù)資料
| 型號(hào)： | DAC5674IPHPR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 23/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 400MSPS 48-HTQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | CommsDAC™ |
| 設(shè)置時(shí)間： | 20ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 550mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-HTQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 400M |
| 配用： | 296-30860-ND - EVAL MODULE FOR DAC5674 |
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DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
3
DC ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 3.3 V, IOVDD = 3.3 V, DVDD = 1.8 V,
IOUTFS = 20 mA, Rset = 1.91 k, internal reference, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESOLUTION
14
Bits
DC ACCURACY(1)
INL
Integral nonlinearity
1 LSB = IOUTFS/214, TMIN to TMAX
3.5
LSB
INL
Integral nonlinearity
1 LSB = IOUTFS/214, TMIN to TMAX
2.14e4
IOUTFS
DNL
Differential nonlinearity
2
LSB
DNL
Differential nonlinearity
1.22e4
IOUTFS
Monotonicity
Montonic to 12 bits
ANALOG OUTPUT
Offset error
0.02
FSR
Gain error
Without internal reference
2.3
%FSR
Gain error
With internal reference
1.3
%FSR
Minimum full-scale output
current(2)
2
mA
Maximum full-scale output
current(2)
20
mA
Output compliance range(3)
IOUTFS = 20 mA
1
1.25
V
Output resistance
300
k
Output capacitance
5
pF
REFERENCE OUTPUT
Reference voltage
1.14
1.2
1.26
V
Reference output current(4)
100
nA
REFERENCE INPUT
VEXTIO
Input voltage range
0.1
1.25
V
Input resistance
1
M
Small signal bandwidth
1.4
MHz
Input capacitance
100
pF
TEMPERATURE COEFFICIENTS
Offset drift
0
ppm of
FSR/
°C
Gain drift
Without internal reference
±50
ppm of
FSR/
°C
Gain drift
With internal reference
±100
ppm of
FSR/
°C
Reference voltage drift
±50
ppm/
°C
POWER SUPPLY
AVDD
Analog supply voltage
3
3.3
3.6
V
DVDD
Digital supply voltage
1.65
1.8
1.95
V
CLKVDD
Clock supply voltage
3
3.3
3.6
V
IOVDD
I/O supply voltage
1.65
3.6
V
PLLVDD
PLL supply voltage
3
3.3
3.6
V
IAVDD
Analog supply current
Including output current through the load
resistor, AVDD = 3.3 V, DVDD = 1.8 V, 4
×
interpolation, PLL on, 9-MHz IF, 400 MSPS
41
55
mA
Specifications subject to change without notice.
(1) Measured differentially across IOUT1 and IOUT2 into 50 .
(2) Nominal full-scale current, IOUTFS, equals 32× the IBIAS current.
(3) The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown, resulting
in reduced reliability of the DAC5674 device. The upper limit of the output compliance is determined by the load resistors and full-scale output
current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
(4) Use an external buffer amplifier with high impedance input to drive any external load.
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