參數(shù)資料
型號： DAC5674IPHPG4
廠商： Texas Instruments
文件頁數(shù)： 11/39頁
文件大?。?/td> 0K
描述： IC DAC 14BIT 400MSPS 48-HTQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標(biāo)準(zhǔn)包裝： 250
系列： CommsDAC™
設(shè)置時間： 20ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 550mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-HTQFP（7x7）
包裝： 托盤
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 400M
配用： 296-30860-ND - EVAL MODULE FOR DAC5674
DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
19
080
IF=32
160
240
320
112
208
0
100
IF=40
200
300
400
260
140
065
IF=26
130
195
260
91
169
”Sinx/x”
Attenuation
Fupdate+65 MSPS
*1.83 dB
*7.2 dB
”Sinx/x”
Attenuation
Fupdate+80 MSPS
*1.83 dB
*7.2 dB
”Sinx/x”
Attenuation
Fupdate+100 MSPS
*1.83 dB
*7.2 dB
Figure 20. High-Pass 4
y Interpolation Filter Operation: Example Frequencies
Clock Generation Function
An internal phase-locked loop (PLL) or external clock can be used to derive the internal clocks (1
×, 2×, and 4×)
for the logic, FIR interpolation filters, and DAC. Basic functionality is depicted in Figure 21. Power for the internal
PLL blocks (PLLVDD and PLLGND) is separate from the other clock generation blocks power (CLKVDD and
CLKGND), thus minimizing phase noise within the PLL. The PLLVDD pin establishes internal/external clock
mode: when PLLVDD is grounded, external clock mode is active and when PLLVDD is 3.3 V, internal clock mode
is active.
In external clock mode, the user provides a differential external clock on pins CLK/CLKC. This clock becomes
the 4
× clock and is twice divided down to generate the 2× and 1× clocks. The 2× or 1× clock is multiplexed out
on the PLLLOCK pin to allow for external clock synchronization.
In internal clock mode, the user provides a differential external reference clock on CLK/CLKC. A type four
phase-frequency detector (PFD) in the internal PLL compares this reference clock to a feedback clock and
drives the PLL to maintain synchronization between the two clocks. The feedback clock is generated by dividing
the VCO output by 1
×, 2×, 4×, or 8×, as selected by the prescaler (DIV[1:0]). The output of the prescaler is the
4
× clock, and is divided down twice to generate the 2× and 1× clocks. Pin X4 selects the 1× or 2× clock to clock
in the input data; the selected clock is also fed back to the PFD for synchronization. The PLLLOCK pin is an
output indicating when the PLL has achieved lock. An external RC low-pass PLL filter is provided by the user
at pin LPF. See the Low-Pass Filter section for filter setting calculations. Table 4 provides a summary of the
clock configurations with corresponding data rate ranges.
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參數(shù)描述
DAC5674IPHP-ND 制造商: 功能描述: 制造商:undefined 功能描述:
DAC5674IPHPR 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14-Bit 400 CommsDAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC5674IPHPRG4 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14-Bit 400 CommsDAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
DAC5675 制造商:TI 制造商全稱:Texas Instruments 功能描述:14-BIT, 400-MSPS DIGITAL-TO-ANALOG CONVERTER
DAC5675A 制造商:TI 制造商全稱:Texas Instruments 功能描述:14-Bit, 400MSPS Digital-to-Analog Converter
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