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參數(shù)資料
| 型號(hào)： | DAC5573IWR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, INTERFACE DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 四，8位，低功耗，電壓輸出，接口數(shù)字，模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 499K |
| 代理商： | DAC5573IWR |
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LDAC Functionality
DAC5573 Registers
DAC5573 as a Slave Receiver—Standard and Fast Mode
Figure 33 shows the standard and fast mode master transmitter addressing a DAC5573
Slave Receiver
with a
7-bit address.
SLAVE ADDRESS R/W
A Ctrl-Byte
A MS-Byte A
LS-Byte
A/A
P
0 (write)
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
From Master to DAC5573
From DAC5573 to Master
A = Acknowledge (SDA LOW)
A = Not Acknowledge (SDA HIGH)
S = START Condition
Sr = Repeated START Condition
P = STOP Condition
DAC5573 I
2
C-SLAVE ADDRESS:
1
0
0
1
1
A1
A0
R/W
MSB
LSB
Factory Preset
A0 = I
2
C Address Pin
A1 = I
2
C Address Pin
S
0 = Write to DAC5573
1 = Read from DAC5573
DAC5573
SLAS401–NOVEMBER 2003
Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal
that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the
channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four
DAC output voltages to be updated simultaneously with temporary register data. The LDAC trigger should only
be used after the buffer's temporary registers are properly updated through software.
Table 3. DAC5573 Architecture Register Descriptions
REGISTER
CTRL[7:0]
MSB[7:0]
TRA[9:0], TRB[9:0],
TRC[9:0], TRD[9:0]
DRA[9:0], DRB[9:0],
DRC[9:0], DRD[9:0]
DESCRIPTION
Stores 8-bit wide control byte sent by the master
Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit power-down data.
10-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 8 LSBs
store data.
10-bit DAC registers for each channel. Two MSBs store power-down information, 8 LSBs store DAC data. An
update of this register means a DAC update with data or power down.
Figure 33. Standard and Fast Mode: Slave Receiver
17
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC5574 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL TO ANALOG CONVERTER |
| DAC5574EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 DAC5574 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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| DAC5574IDGS | 制造商:Texas Instruments 功能描述:IC DAC 8BIT 188KSPS MSOP-10 |
| DAC5574IDGSG4 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 8-bit Quad Converter with I2C interface RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
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