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參數(shù)資料
| 型號： | DAC3550A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | DAC |
| 英文描述： | ECONOLINE: RSZ/P - 1kVDC |
| 中文描述： | 32-BIT DAC, PQFP44 |
| 封裝： | METRIC, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 9/35頁 |
| 文件大?。?/td> | 626K |
| 代理商： | DAC3550A |
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DAC 3550A
Micronas
9
2.11. I
2
C Bus Interface
The DAC 3550A is equipped with an I
2
C bus slave
interface. The I
2
C bus interface uses one level of sub-
addressing: The I
2
C bus address is used to address
the IC. The subaddress allows chip select in multi DAC
applications and selects one of the three internal regis-
ters. The registers are write-only. The I
2
C bus chip
address is given below.
dev_write = $9A.
The registers of the DAC 3550A have 8- or 16-bit data
size; 16-bit registers are accessed by writing two 8-bit
data words.
Fig. 2
–
6:
I
2
C bus protocols for write operations
2.12. Registers
In Section 3.6.
“
Control Registers
”
on page 15, a defi-
nition of the DAC 3550A control registers is shown. A
hardware reset initializes all control registers to 0. The
automatic chip initialization loads a selected set of reg-
isters with the default values given in the table.
All registers are write-only.
The register address is coded by 3 bits (RA1, RA0)
according to Table 2
–
3.
The mnemonics used in the DAC 3550A demo soft-
ware of Micronas are given in the last column.
2.13. Chip Select
Chip select allows to connect up to four DAC 3550A to
an I
2
C control bus. The chip subaddresses are defined
by the MCS1/MCS2 (Mode and Chip Select) pins. Only
in standard mode, chip select is possible. MPEG mode
always uses chip subaddress 3.
Register address and chip select are mapped into the
subaddress field in Table 2
–
4.
2.14. Reduced Feature Mode
If I
2
C control is not used, the IC is in the default mode
(see Section 3.6.
“
Control Registers
”
on page 15) after
start-up. Default Volume setting is 0 dB and digital
audio input is set to standard I
2
S. Sample rates from
32 kHz to 48 kHz are supported in this mode. Applica-
tions with no need for volume control or analog input
could use this mode.
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
1
1
0
1
0
8-bit I
2
C write access
SDA
SCL
1
0
S
P
Start
Stop
W
R
Ack
Nak
S
P
=
=
=
=
=
=
1
0
1
0
1 byte data
S
dev_write
Ack sub_adr
Ack
Ack P
S dev_write Ack sub_adr Ack 1 byte data Ack 1 byte data Ack P
16-bit I
2
C write access
Table 2
–
3:
I
2
C Register Address
RA1
RA0
Mnemonics
0
1
SR_REG
1
0
AVOL
1
1
GCFG
Table 2
–
4:
I
2
C Subaddress
7
6
5
4
3
2
1
0
MCS2
MCS1
RA1
RA0
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