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參數(shù)資料
| 型號： | DAC1628D1G25HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: JESD204B interface: up to 1.25 Gsps; 2x, 4x and 8x interpolating |
| 封裝： | DAC1628D1G25HN/C1<SOT684-8 (HVQFN56)|<<http://www.nxp.com/packages/SOT684-8.html<1<Always Pb-free,;DAC1628D1G25HN/C1<SOT684-8 (HVQFN56)|<<http://www.nxp.com/packages/SOT6 |
| 文件頁數(shù)： | 1/133頁 |
| 文件大?。?/td> | 1961K |
| 代理商： | DAC1628D1G25HN |
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1. General description
The DAC1628D1G25 is a high-speed high-performance 16-bit dual channel
digital-to-analog converter (DAC). The device provides a sample rate up to 1.25 Gsps
with
selectable 2
, 4
and 8
interpolation filters optimized for multi-carrier and broadband
wireless transmitters.
The DAC1628D1G25 integrates a CVGxpress high-speed serial input data interface
running up to 6.25 Gbps allowing dual channel input sampling at up to 625 Msps over four
differential lanes. CGVXpress is fully compliant with the JEDEC JESD204B standard. It
offers numerous advantages over traditional parallel digital interfaces:
Easier Printed-Circuit Board (PCB) layout
Lower radiated noise
Lower pin count
Self-synchronous link
Skew compensation
Deterministic latency
Multiple Device Synchronization (MDS)
Harmonic clocking support
Assured FPGA interoperability
An optional on-chip digital modulation converts the complex I/Q pattern from baseband to
IF. The mixer frequency is set by writing to the Serial Peripheral Interface (SPI) control
registers associated with the on-chip 40-bit Numerically Controlled Oscillator (NCO). This
accurately places the IF carrier in the frequency domain. The 16-bit phase adjustment
feature, the 12-bit digital gain and the 16-bit digital offset enable full control of the analog
output signals.
The DAC1628D1G25 is fully compliant with device subclass 1 of the JEDEC JESD204B
standard, guaranteeing deterministic and repeatable interface latency using the
differential SYSREF signal. The device also supports harmonic clocking to reduce
system-level clock synthesis and distribution challenges.
Multiple Device Synchronization (MDS, a unique CGVxpress feature) enables up to
16 DAC channels to be sample synchronous and phase coherent to within one DAC clock
period. MDS is ideal for LTE and LTE-A MIMO transceiver applications.
DAC1628D1G25
Dual 16-bit DAC: JESD204B interface: up to 1.25 Gsps; x2, x4
and x8 interpolating
Rev. 1.1 — 10 October 2011
Objective data sheet
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