參數(shù)資料
型號: DAC1403D160
廠商: NXP Semiconductors N.V.
中文描述: Demoboard description Demo box contents CDROM (datasheets, PCB layout-schematics, Quickstart guide) Extension module Clock generator; pattern generator for DAC (HSDC-EXTMOD01-DB) Data Acquisition for ADC with CMOS outputs mode (HSDC-EXTMOD01-DB),
文件頁數(shù): 10/19頁
文件大?。?/td> 113K
代理商: DAC1403D160
DAC1403D160_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 14 August 2008
10 of 19
NXP Semiconductors
DAC1403D160
Dual 14 bits DAC, up to 160 MHz, 2 x interpolating
[1]
Guaranteed by design.
Signal-to-noise ratio
S/N
signal-to-noise ratio
f
clk
= 80 MHz; BW = Nyquist
f
o
= 2.5 MHz
f
o
= 5 MHz
f
o
= 19 MHz
baseband; 5 MHz channel spacing; BW = 3.84 MHz
f
o
= 2.5 MHz
f
o
= 20 MHz
-
70
-
80
80
78
-
-
-
dBc
dBc
dBc
ACPR
adjacent channel power
ratio
-
-
69
71
-
-
dBc
dBc
Table 5.
V
CCD
= V
CCA
= 3.0 V to 3.6 V; AGND and DGND connected together; T
amb
=
40
°
C to +85
°
C; typical values measured at
V
CCD
= V
CCA
= 3.3 V I
O(fs)
= 20 mA and T
amb
= 25
°
C; dynamic parameters measured using output schematic given in
Figure 10
; unless otherwise specified.
Symbol
Parameter
Conditions
Characteristics
…continued
Min
Typ
Max
Unit
Table 6.
Band gap disable (GAPD)
LOW
HIGH
Band gap
Band gap input/output (GAPOUT)
output (V
GAPOUT
= 1.2 V)
input
Internal band gap
enable
disable
Fig 5.
Input timing diagram
014aaa511
Q0 to Q13
t
su(i)
t
h(i)
CLKN
CLK
IOUT/IOUTN,
QOUT/QOUTN
50 %
I0 to I13,
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