
77
2588F–AVR–06/2013
ATtiny261/461/861
OCF0B, but in 16-bit mode the match can set only the Output Compare Flag OCF0A as there is
only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Compare
Flag generates an Output Compare interrupt. The Output Compare Flag is automatically cleared
when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a log-
ical one to its I/O bit location.
Figure 11-5 shows a block diagram of the Output Compare unit.
Figure 11-5.
Output Compare Unit, Block Diagram
11.6.1
Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0H/L Register will block any Compare Match that occur in
the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A/B to be
initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter
clock is enabled.
11.6.2
Using the Output Compare Unit
Since writing TCNT0H/L will block all Compare Matches for one timer clock cycle, there are risks
involved when changing TCNT0H/L when using the Output Compare Unit, independently of
whether the Timer/Counter is running or not. If the value written to TCNT0H/L equals the
OCR0A/B value, the Compare Match will be missed.
11.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the Timer/Counter Width (TCW0), Input Capture Enable (ICEN0) and Wave Genera-
Table 11-3 summarises the different modes of operation.
OCFnx (Int.Req.)
= (8/16-bit Comparator )
OCRnx
DATA BUS
TCNTn
Table 11-3.
Modes of operation
Mode
ICEN0
TCW0
CTC0
Mode of Operation
TOP
Update of OCRx at
TOV Flag Set on
0000
Normal, 8-bit Mode
0xFF
Immediate
MAX (0xFF)
1001
CTC Mode, 8-bit
OCR0A
Immediate
MAX (0xFF)
2
0
1
X
Normal, 16-bit Mode
0xFFFF
Immediate
MAX (0xFFFF)
3
1
0
X
Input Capture Mode, 8-bit
0xFF
Immediate
MAX (0xFF)
4
1
X
Input Capture Mode, 16-bit
0xFFFF
Immediate
MAX (0xFFFF)