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參數(shù)資料
| 型號(hào)： | D485505G |
| 廠商： | NEC Corp. |
| 英文描述： | LINE BUFFER 5K-WORD BY 8-BIT |
| 中文描述： | 行緩沖區(qū)5K - Word的8位 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 174K |
| 代理商： | D485505G |
1994,1996
DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD485505
Description
The
μ
PD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer. Its CMOS static circuitry
provides high speed access and low power consumption.
The
μ
PD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and
digital copiers.
Moreover, the
μ
PD485505 can execute read and write operations independently on an asynchronous basis. Thus
the
μ
PD485505 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for
the synchronization of multiple input signals. There are three versions, E, K, P, and L. This data sheet can be applied
to the version P and L. These versions operate with different specifications. Each version is identified with its lot
number (refer to
7. Example of Stamping
).
Features
5,048 words by 8 bits
Asynchronous read/write operations available
Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns)
15 to 5,048 bits (Cycle time: 35 ns)
Power supply voltage V
CC
= 5.0 V
±
0.5 V
Suitable for sampling one line of A3 size paper (16 dots/mm)
All input/output TTL compatible
3-state output
Full static operation; data hold time = infinity
Ordering Information
Part Number
R/W Cycle Time
Package
μ
PD485505G-25
25 ns
24-pin plastic SOP
(11.43 mm (450))
μ
PD485505G-35
35 ns
LINE BUFFER
5K-WORD BY 8-BIT
The mark shows major revised points.
Document No. M10059EJ7V0DSJ1 (7th edition)
Date Published December 2000 N CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
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