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參數(shù)資料
| 型號： | CYW173SXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 1/5頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN TAPE DRV 4CH 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | CPB Tape Drive System |
| 輸入： | 晶體 |
| 輸出： | TTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:4 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 100MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
Tape Drive Frequency Timing Generator
W173
..........Document #: 38-07313 Rev. *B Page Page 1 of 5 of 5
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
Features
Four derived outputs at frequencies specified by
Hewlett Packard Computer Peripherals Bristol/Boise
(CPB)
Less than ±250 ps cycle-to-cycle jitter
(13.2 MHz clock excluded derated to ±400 ps)
Less than ±350 ps absolute jitter
Supports 3.3V operation
TTL compatible logic: VIL = 0.8V max., VIH = 2.0V min.,
VOL = 0.4V max., and VOH = 2.4V min.
OE pin has internal pull-up
45/55% duty cycle on all outputs
15
output drivers
Accepts 26.5625 MHz input reference
Built-in crystal oscillator circuit. Capacitive load
presented to the crystal is approximately 14 pF
Outputs designed to drive 30 pF loads
Available in 16-pin SOIC package
Functional Description
The W173 has been defined to meet the timing signal require-
ments for Hewlett Packard CPB tape drive system.
S
Block Diagram
Pin Configuration
XTAL
OSC
REFIN
PLL 1
50 MHz
6.6 MHz
13.2 MHz
PLL 2
OE
10 MHz
VDD
6.6MHZ
GND
13.2MHZ
VDD
GND
10MHZ
16
15
14
13
12
11
10
VDD
X1
X2
GND
OE
VDD
50MHZ
1
2
3
4
5
6
7
8
9
VDD
GND
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