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參數(shù)資料
型號： CYW150OXC
廠商： Silicon Laboratories Inc
文件頁數(shù)： 3/14頁
文件大?。?/td> 0K
描述： IC CLOCK 440BX AGP 56SSOP
標準包裝： 26
類型： 時鐘/頻率合成器，擴展頻譜時鐘發(fā)生器
PLL： 是
主要目的： Intel CPU 服務器
輸入： 時鐘，晶體
輸出： 時鐘
電路數(shù)： 1
比率 - 輸入:輸出： 2:33
差分 - 輸入:輸出： 無/無
頻率 - 最大： 150MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 56-BSSOP（0.295"，7.50mm 寬）
供應商設備封裝： 56-SSOP
包裝： 管件
CYW150
...................... Document #: 38-07177 Rev. *B Page 11 of 14
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two
adjacent cycles.
250
ps
tSK
Output Skew
Measured on rising edge at 1.5V
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
1.5
4
ns
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior
to frequency stabilization.
3ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination
value.
15
IOAPIC0 and IOAPIC_F Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.6/100 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.31818
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.25V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5
ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
15
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.6/100 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
25
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.8 MHz
CPU = 100 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
t
P
Period
Measured on rising edge at 1.5V
15
15.5
10
10.5
ns
tH
High Time
Duration of clock cycle above 2.4V
5.2
3.0
ns
tL
Low Time
Duration of clock cycle below 0.4V
5.0
2.0
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
4
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
1
4
V/ns
PCI Clock Outputs, PCI_F and PCI0:5 (Lump Capacitance Test Load = 30 pF) (continued)
Parameter
Description
Test Condition/Comments
CPU = 66.6/100 MHz
Unit
Min.
Typ.
Max.
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