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參數(shù)資料
| 型號： | CYM52KQT36AV25 |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁數(shù)： | 5/25頁 |
| 文件大?。?/td> | 245K |
| 代理商： | CYM52KQT36AV25 |
CYM52KQT36AV25
ADVANCE INFORMATION
Document #: 38-05041 Rev. **
Page 5 of 25
Single Clock Mode
The CYM52KQT36AV25 can be used with a single clock
mode. In this mode the device will recognize only the pair of
input clocks (K and K) that control both the input and output
registers. This operation is identical to the operation if the de-
vice had zero skew between the K/K and C/C clocks. All timing
parameters remain the same in this mode. To use this mode
of operation, the user must tie C and C to V
DD
. During pow-
er-up, the device will sense the single clock input and operate
in either single clock or double clock mode. The clock mode
should not be changed during device operation.
Concurrent Transactions
The Read and Write ports on the CYM52KQT36AV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the transac-
tion on the other port. Should the Read and Write ports access
the same location on the rising edge of the positive input clock,
the information presented to D
[35:0]
will be forwarded to Q
[35:0]
such that no latency is required to access valid data. Coher-
ency is conducted on cycle boundaries. Once the second word
of data is latched into the device, the write operation is consid-
ered completed. At this point, any access to that address loca-
tion will receive that data until altered by a subsequent Write
operation. Coherency is not maintained for Write operations
initiated in the cycle after a Read.
Depth Expansion
The CYM52KQT36AV25 has a Port Select input for
each port. This allows for easy depth expansion. Both
Port Selects are sampled on the rising edge of the pos-
itive input clock only (K). Each port select input can de-
select the specified port. Deselecting a port will not af-
fect the other port. All pending transactions (Read and
Write) will be completed prior to the device being dese-
lected.
Programmable Impedance
An external resistor, RQ, must be connected between
the ZQ pin on the SRAM and V
SS
to allow the SRAM to
adjust its output driver impedance. The value of RQ
must be 5X the value of the intended line impedance
driven by the SRAM. The allowable range of RQ to guar-
antee impedance matching with a tolerance of ±10% is
between 175
and 350
, with V
DDQ
= 1.5V. The output
impedance is adjusted every 1024 cycles to adjust for
drifts in supply voltage and temperature.
Truth Table
[
1,2
]
Operation
Address
used
RPS
WPS
K
Comments
Deselected
-
H
H
L-H
Read Port is deselected. Outputs three-state following next rising edge of
negative input clock (K) if in single clock mode, or C if using C and C as
the output clocks.
Write Port is deselected. All Write Port inputs are ignored during this clock
rise and the subsequent rising edge of the negative input clock (K).
Begin Read
External
L
H
L-H
Read operation initiated. Addresses are stored in the Read Address Reg-
ister. Following the next K clock rise the first (lower order) 36-bit word will
be available to be driven out onto Q
[35:0]
gated by the rising edge of the
output clock C. On the subsequent rising edge of the negative output clock
(C) the second (higher order) 36-bit word is driven out onto Q
[35:0]
.
Begin Write
External
on next
rising
edge of K
H
L
L-H
Write operation initiated. The information presented to D
[35:0]
is stored in
the Write Data Register. On the subsequent rising edge of the negative
input clock (K) the device will latch the addresses presented to A
[17:0]
and
the data presented to D
[35:0]
]. The entire 72 bits of information will then
be written into the memory array. See Write Description table for byte write
information,
Note:
1.
2.
3.
4.
5.
X = Don
’
t Care, H = Logic HIGH, L = Logic LOW.
Device will power-up deselected and the outputs in a three-state condition.
BWS
and BWS
asserted active LOW during all cycles. For byte write operations, see Write Description Table.
Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
It is recommended that K = K# and C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
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