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參數(shù)資料
| 型號(hào)： | CYK001M16SCCAU |
| 英文描述： | Memory |
| 中文描述： | 內(nèi)存 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大?。?/td> | 168K |
| 代理商： | CYK001M16SCCAU |
ADVANCE
INFORMATION
CYK001M16SCCAU
MoBL
Document #: 38-05426 Rev. **
Page 5 of 10
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[12, 13]
WE HIGH to Low Z
[12, 13]
55
0
0
55
55
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
5
Switching Characteristics
(Over the Operating Range) (continued)
[11]
Parameter
Description
CYK001M16SCCAU-70
Min.
Unit
Max.
Switching Waveforms
Note:
15.WE is HIGH for Read Cycle.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
tRC
tAA
tOHA
Read Cycle 1 (Address Transition Controlled)
[15]
tSK
Read Cycle No. 2 (OE Controlled)
[15]
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tPD
HIGH
IMPEDANCE
OE
CE
1
I
CC
ADDRESS
CE2
VCC
tHZBE
BHE
/
BLE
tLZBE
tHZCE
DATA OUT
tDBE
tSK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYK001M16ZCCAU | Memory |
| CYK512K16SCCAU | Memory |
| CYL2T0201-AIP | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| CYM1910PV-25C | SYNC SRAM|16KX68|CMOS|DIP|104PIN|PLASTIC |
| CYM1910PV-35C | SYNC SRAM|16KX68|CMOS|DIP|104PIN|PLASTIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYK001M16SCCAU-55BAI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
| CYK001M16SCCAU-55BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 55NS 48FBGA - Tape and Reel |
| CYK001M16SCCAU-70BAI | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 70NS 48FBGA - Bulk |
| CYK001M16SCCAU-70BAIT | 制造商:Cypress Semiconductor 功能描述:SRAM ASYNC SGL 3V 16MBIT 1MX16 70NS 48FBGA - Tape and Reel |
| CYK001M16ZCCA | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:16-Mbit (1M x 16) Pseudo Static RAM |
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