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參數(shù)資料
| 型號： | CY7C43626 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256 x36/x18x2 Tri Bus FIFO(256 x36/x18x2 三路總線先進先出) |
| 中文描述： | 256 x36/x18x2三總線的FIFO（256 x36/x18x2三路總線先進先出） |
| 文件頁數(shù)： | 1/40頁 |
| 文件大?。?/td> | 577K |
| 代理商： | CY7C43626 |
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CY7C43626
CY7C43636/CY7C43646
CY7C43666/CY7C43686
PRELIMINARY
256/512/1K/4K/16K x36/x18x2 Tri Bus FIFO
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
September 22, 1999
Features
High-speed, low-power, first-in first-out (FIFO) memo-
ries w/ three independent ports (one bidirectional x36,
and two unidirectional x18)
256 x36/x18x2 (CY7C43626)
512 x36/x18x2 (CY7C43636)
1K x36/x18x2 (CY7C43646)
4K x36/x18x2 (CY7C43666)
16K x36/x18x2 (CY7C43686)
0.35-micron CMOS for optimum speed/power
High speed 133-MHz operation (7.5-ns read/write cycle
times)
Low power
—I
CC
= 100 mA
—I
SB
= 10 mA
Fully asynchronous and simultaneous read and write
operation permitted
Mailbox bypass register for each FIFO
Parallel and Serial Programmable Almost Full and
Almost Empty flags
Retransmit function
Standard or FWFT mode user selectable
Partial Reset
Big or Little Endian format for word or byte bus sizes
128-pin TQFP packaging
Pin-compatible, feature enhanced, density upgrade to
IDT723626/36/46 family
Easily expandable in width and depth
Logic Block Diagram
Port A
Control
Logic
Port B
Control
Logic
Mail1
Register
I
R
Write
Pointer
Read
Pointer
Status
Flag Logic
Programmable
Flag Offset
Registers
Timing
Mode
Status
Flag Logic
Read
Pointer
Write
Pointer
256/512/1K
4K/16K x36
Dual Ported
Memory
256/512/1K
4K/16K x36
Dual Ported
Memory
Mail2
Register
O
R
I
R
FIFO1,
Mail1
Reset
Logic
FIFO2,
Mail2
Reset
Logic
CLKA
CSA
W/RA
ENA
MBA
RT2
MRS1
PRS1
FFA/IRA
AFA
SPM
FS0/SD
FS1/SEN
A
0
35
EFA/ORA
AEA
MBF2
MRS2
PRS2
FFC/IRC
AFC
BE/FWFT
B
0
17
CLKB
RENB
CSB
SIZEB
MBB
RTI
EFB/ORB
AEB
MBF1
O
R
B
Common
Port Logic
(B and C)
BE
O
C
0
17
Port C
Control
Logic
CLKC
WENC
MBC
SIZEC
B
I
相關PDF資料 |
PDF描述 |
|---|---|
| CY7C43646 | 1K x36/x18x2 Tri Bus FIFO(1K x36/x18x2 三路總線 先進先出) |
| CY7C43666 | 4K x36/x18x2 Tri Bus FIFO(4K x36/x18x2 三路總線先進先出) |
| CY7C43686 | 16K x36/x18x2 Tri Bus FIFO(16K x36/x18x2 三路總線先進先出) |
| CY7C43662AV | 3.3V 4K x36 x2 Bidirectional Synchronous FIFO(3.3V 4K x36 x2 雙向同步先進先出) |
| CY7C43682AV | 3.3V 16K x36 x2 Bidirectional Synchronous FIFO(3.3V 16K x36 x2 雙向同步先進先出) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C43642-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP |
| CY7C43643-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CY7C43643AV-10AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-15AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
| CY7C43643AV-7AC | 制造商:Cypress Semiconductor 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 36 128-Pin TQFP |
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