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參數(shù)資料
| 型號(hào)： | CY7C344B-20HC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | UV PLD, 20 ns, CQCC28 |
| 封裝： | WINDOWED, CERAMIC, LCC-28 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 394K |
| 代理商： | CY7C344B-20HC |
USE ULTRA37000 FOR
ALL NEW DESIGNS
CY7C344B
Document #: 38-03036 Rev. *D
Page 4 of 12
Figure 1. CY7C344B Timing Model
LOGIC ARRAY
CONTROLDELAY
tLAC
EXPANDER
DELAY
t EXP
CLOCK
DELAY
tIC
tRD
tCOMB
tLATCH
INPUT
DELAY
tIN
REGISTER
OUTPUT
DELAY
tOD
tXZ
tZX
LOGIC ARRAY
DELAY
tLAD
FEEDBACK
DELAY
tFD
OUTPUT
INPUT
SYSTEM CLOCK DELAYtICS
tRH
tRSU
tPRE
tCLR
I/O
I/O DELAY
tIO
I/O
External Synchronous Switching Characteristics Over Operating Range
Parameter
Description
7C344B-15
7C344B-20
7C344B-25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tPD1
Dedicated Input to Combinatorial Output Delay[5] Com’l/Ind
15
20
25
ns
tPD2
I/O Input to Combinatorial Output Delay[5]
Com’l/Ind
15
20
25
ns
tSU
Global Clock Set-up Time
Com’l/Ind
9
12
15
ns
tCO1
Synchronous Clock Input to Output Delay[5]
Com’l/Ind
10
12
15
ns
tH
Input Hold Time from Synchronous Clock Input
Com’l/Ind
0
ns
tWH
Synchronous Clock Input HIGH Time
Com’l/Ind
6
7
8
ns
tWL
Synchronous Clock Input LOW Time
Com’l/Ind
6
7
8
ns
fMAX
Maximum Register Toggle Frequency[6]
Com’l/Ind
83.3
71.4
62.5
MHz
tCNT
Minimum Global Clock Period
Com’l/Ind
13
16
20
ns
tODH
Output Data Hold Time After Clock
Com’l/Ind
1
ns
fCNT
Maximum Internal Global Clock Frequency[7]
Com’l/Ind
76.9
62.5
50
MHz
Notes:
5. C1 = 35 pF
6. The fMAX values represent the highest frequency for pipeline data.
7. This parameter is measured with a 32-bit counter programmed into each LAB.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C344B-20HI | UV PLD, 20 ns, CQCC28 |
| CY7C344B-25HC | UV PLD, 25 ns, CQCC28 |
| CY7C344B-25HI | UV PLD, 25 ns, CQCC28 |
| CY7C346-35RM | UV PLD, CPGA100 |
| CY7C346-35HM | UV PLD, CQCC84 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C344B-20WC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 600 Gates 32 Macro Cells 62.5MHz 0.65um Technology 5V 28-Pin Windowed CDIP |
| CY7C346-25JC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 0.8um Technology 5V 84-Pin PLCC |
| CY7C346-35HI | 制造商:QP Semiconductor 功能描述:CYP BIN-7C346A 35NS-LCC-I/T |
| CY7C346-35RI | 制造商:QP Semiconductor 功能描述: |
| CY7C346B-25NC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 2.5K Gates 128 Macro Cells 50MHz 0.65um Technology 5V 100-Pin PQFP |
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