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參數資料
| 型號： | CY7C128A-45LMB |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 2K x 8 Static RAM |
| 中文描述： | 2K X 8 STANDARD SRAM, 45 ns, CQCC24 |
| 封裝： | LCC-24 |
| 文件頁數： | 1/9頁 |
| 文件大?。?/td> | 217K |
| 代理商： | CY7C128A-45LMB |
2K x 8 Static RAM
CY7C128A
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
December 1988 – Revised December 1992
1CY7C128A
Features
Automatic power-down when deselected
CMOS for optimum speed/power
High speed
—15 ns
Low active power
—440 mW (commercial)
—550 mW (military)
Low standby power
—110 mW
TTL-compatible inputs and outputs
Capable of withstanding greater than 2001V electro-
static discharge
V
IH
of 2.2V
Functional Description
The CY7C128A is a high-performance CMOS static RAM or-
ganized as 2048 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), and active LOW
output enable (OE) and three-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
Writing to the device is accomplished when the chip enable
(CE) and write enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O
0
through I/O
7
) is written into the
memory location specified on the address pins (A
0
through
A
10
).
Reading the device is accomplished by taking chip enable
(CE) and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory location
specified on the address pins will appear on the eight I/O pins.
The I/O pins remain in high-impedance state when chip enable
(CE) or output enable (OE) is HIGH or write enable (WE) is LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
Logic Block Diagram
Pin Configurations
C128A–1
A
1
A
2
A
4
A
5
A
6
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
Top View
LCC
1
2
3
4
5
6
7
8
9
10
11
12
14
13
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
A
6
A
5
A
4
A
3
A
2
A
1
A
0
WE
OE
V
CC
A
8
A
9
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
C128A–2
A
7
I/O
0
I/O
1
I/O
2
GND
128 x 16 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
7C128A
A
0
C128A–3
A
3
A
7
A
8
A
9
A
10
24
4
5
6
7
8
9
10
3 2 1
23
11 12 13 14 15
22
21
20
19
18
17
16
7C128A
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
WE
OE
A
10
CE
I/O
7
I/O
6
A
9
Selection Guide
7C128A–15
15
120
7C128A–20
20
100
125
40/20
40/20
7C128A–25
25
100
125
20
40
7C128A–35
35
100
100
20
20
7C128A–45
45
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Commercial
Military
Commercial
Military
100
Maximum Standby
Current (mA)
40/40
20
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