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參數資料
| 型號： | CY7C123 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256 x 4 Static RAM(256 x 4 靜態(tài) RAM) |
| 中文描述： | 256 × 4靜態(tài)RAM（256 × 4靜態(tài)內存） |
| 文件頁數： | 1/9頁 |
| 文件大?。?/td> | 138K |
| 代理商： | CY7C123 |
256 x 4 Static RAM
CY7C123
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
January 1989 - Revised December 1992
Features
256 x 4 static RAM for control store in high-speed
computers
CMOS for optimum speed/power
High speed
—7 ns (commercial)
—10 ns (military)
Low power
—660 mW (commercial)
—825 mW (military)
Separate inputs and outputs
5-volt power supply
±
10% tolerance both commercial
and military
TTL-compatible inputs and outputs
24 pins
300-mil package
Functional Description
The CY7C123 is a high-performance CMOS static RAM orga-
nized as 256 words by 4 bits. Easy memory expansion is pro-
vided by an active LOW chip select one (CS
1
) input, an active
HIGH chip select two (CS
2
) input, and three-state outputs.
Writing to the device is accomplished when the chip select one
(CS
1
) and write enable (WE) inputs are both LOW and the chip
select two input is HIGH. Data on the four data inputs (D
0
through D
3
) is written into the memory location specified on
the address pins (A
0
through A
7
). The outputs are precondi-
tioned so that the write data is present at the outputs when the
write cycle is complete. This precondition operation ensures
minimum write recovery times by eliminating the “write recov-
ery glitch.”
Reading the device is accomplished by taking the chip select
one (CS
1
) and output enable (OE) inputs LOW, while the write
enable (WE) and chip select two (CS
2
) inputs remain HIGH.
Under these conditions, the contents of the memory location
specified on the address pins will appear on the four output
pins (O
0
through O
3
).
The output pins remain in high-impedance state when chip
select one (CS
1
) or output enable (OE) is HIGH, or write en-
able (WE) or chip select two (CS
2
) is LOW.
A die coat is used to insure alpha immunity.
COLUMN
DECODER
Logic Block Diagram
Pin Configuration
C123–1
16 x 64
ARRAY
A
0
A
1
A
2
A
3
R
S
DATA INPUT
CONTROL
O
0
O
1
O
2
O
3
A
4
A
5
A
6
A
7
D
0
D
1
D
2
D
3
OE
WE
CS
1
CS
2
C123–2
O
1
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
14
13
15
16
20
19
18
17
21
24
23
22
Top View
DIP/SOJ
A
2
A
3
A
4
A
5
A
6
A
7
V
SS
D
0
D
1
O
0
O
2
V
CC
A
1
A
0
WE
CS
1
OE
V
CC
CS
2
D
3
D
2
O
3
Selection Guide
7C123–7
7
7C123–9
9
7C123–10
7C123–12
12
12
120
150
7C123–15
Maximum Access Time (ns)
Commercial
Military
Commercial
Military
10
15
Maximum Operating Current (mA)
120
120
150
150
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