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參數(shù)資料
| 型號： | CY7C109D |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 1-Mbit (128K x 8) Static RAM |
| 中文描述： | 1兆位（128K的× 8）靜態(tài)RAM |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 919K |
| 代理商： | CY7C109D |
CY7C109D
CY7C1009D
1-Mbit (128K x 8) Static RAM
Cypress Semiconductor Corporation
Document #: 38-05468 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised February 22, 2007
Features
Pin- and function-compatible with CY7C109B/CY7C1009B
High speed
— t
AA
= 10 ns
Low active power
— I
CC
= 80 mA @ 10 ns
Low CMOS standby power
— I
SB2
= 3 mA
2.0V Data Retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
1
, CE
2
and OE options
CY7C109D available in Pb-free 32-pin 400-Mil wide Molded
SOJ and 32-pin TSOP I packages. CY7C1009D available
in Pb-free 32-pin 300-Mil wide Molded SOJ package
Functional Description
[1]
The CY7C109D/CY7C1009D is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE
1
), an active HIGH Chip Enable (CE
2
), an active LOW
Output Enable (OE), and tri-state drivers.The eight input and
output pins (IO
0
through IO
7
) are placed in a high-impedance
state when:
Deselected (CE
1
HIGH or CE
2
LOW),
Outputs are disabled (OE HIGH),
When the write operation is active (CE
1
LOW, CE
2
HIGH,
and WE LOW)
Write to the device by taking Chip Enable One (CE
1
) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE
2
) input
HIGH. Data on the eight IO pins (IO
0
through IO
7
) is then
written into the location specified on the address pins (A
0
through A
16
).
Read from the device by taking Chip Enable One (CE
1
) and
Output Enable (OE) LOW while forcing Write Enable (WE) and
Chip Enable Two (CE
2
) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
appears on the IO pins.
Logic Block Diagram
IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
S
POWER
DOWN
WE
OE
A0
A1
A2
A3
A4
A5
A6
A7
A8
R
128K x 8
ARRAY
INPUT BUFFER
CE1
CE2
A
A
A
A
A
A
A
A
COLUMN DECODER
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at
www.cypress.com
.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C109D-10VXI | 功能描述:靜態(tài)隨機存取存儲器 1M 512K IND FAST ASYNC 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C109D-10VXI | 制造商:Cypress Semiconductor 功能描述:IC SRAM 1MBIT PARALLEL 10NS SOJ-32 |
| CY7C109D10VXIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 10ns 32-Pin SOJ T/R |
| CY7C109D-10VXIT | 功能描述:靜態(tài)隨機存取存儲器 1M 512K IND FAST ASYNC 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C109D10ZXI | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 10ns 32-Pin TSOP-I |
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