參數(shù)資料
型號(hào)： CY7C1049DV33-12VXE
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： DRAM
英文描述： 4-Mbit (512K x 8) Static RAM
中文描述： 512K X 8 STANDARD SRAM, 12 ns, PDSO36
封裝： 0.400 INCH, LEAD FREE, SOJ-36
文件頁(yè)數(shù)： 1/8頁(yè)
文件大?。?/td> 432K
代理商： CY7C1049DV33-12VXE
4-Mbit (512K x 8) Static RAM
CY7C1049DV33
Cypress Semiconductor Corporation
Document #: 38-05475 Rev. *C
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised April 3, 2006
Features
Pin- and function-compatible with CY7C1049CV33
High speed
— t
AA
= 10 ns
Low active power
— I
CC
= 90 mA @ 10 ns (Industrial)
Low CMOS standby power
— I
SB2
= 10 mA
2.0V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Available in Lead-Free 36-lead (400-mil) Molded SOJ
V36 and 44-pin TSOP II ZS44 packages
Functional Description
[1]
The CY7C1049DV33 is a high-performance CMOS Static
RAM organized as 512K words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. Writing
to the device is accomplished by taking Chip Enable (CE) and
Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
) is then written into the location specified on the
address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1049DV33 is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
1
A
1
A
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
COLUMN
R
S
INPUTBUFFER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
CE
A
1
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
23
22
24
28
27
26
25
29
32
31
30
Top View
SOJ
33
36
35
34
16
17
21
20
GND
I/O
2
I/O3
A
1
A
2
A
3
A
4
CE
A
5
A
6
A
7
A
8
A
9
WE
V
CC
I/O
5
I/O
4
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
14
A
13
A
0
I/O
0
I/O
1
V
CC
A
1
18
19
GND
A
10
NC
NC
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
TSOP II
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
2
I/O
3
NC
NC
A
0
A
1
A
2
A
18
A
17
A
16
V
SS
V
CC
I/O
5
I/O
4
A
14
A
13
NC
NC
A
15
OE
I/O
7
I/O
6
A
3
A
4
CE
I/O
0
I/O
1
A
12
A
11
A
10
NC
NC
18
19
20
21
27
26
25
24
22
23
NC
WE
A
5
NC
Selection Guide
-10 (Industrial)
10
90
10
-12 (Automotive)
[2]
12
95
15
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Notes:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
2. Automotive product information is Preliminary.
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