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參數(shù)資料
| 型號(hào)： | CY7C1049BN-12VC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 8 Static RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 12 ns, PDSO36 |
| 封裝： | 0.400 INCH, SOJ-36 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大小： | 451K |
| 代理商： | CY7C1049BN-12VC |
512K x 8 Static RAM
CY7C1049BN
Cypress Semiconductor Corporation
Document #: 001-06501 Rev. **
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised February 2, 2006
1CY7C1049BN
Features
High speed
— t
AA
= 12 ns
Low active power
— 1320 mW (max.)
Low CMOS standby power (Commercial L version)
— 2.75 mW (max.)
2.0V Data Retention (400
μ
W at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
[1]
The CY7C1049BN is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1049BN is available in a standard 400-mil-wide
36-pin SOJ package with center power and ground (revolu-
tionary) pinout.
1
A
1
A
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
COLUMN
DECODER
R
S
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
I/O
1
I/O
2
I/O
3
512K x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
0
A
1
A
1
A
1
CE
A
1
A
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
23
22
24
28
27
26
25
29
32
31
30
Top View
SOJ
33
36
35
34
16
17
21
20
GND
I/O
2
I/O3
A
1
A
2
A
3
A
4
CE
A
5
A
6
A
7
A
8
A
9
WE
V
CC
I/O
5
I/O
4
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
A
12
A
11
A
14
A
13
A
0
I/O
0
I/O
1
V
CC
A
1
18
19
GND
A
10
NC
NC
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C1049BN-12VXC | 512K x 8 Static RAM |
| CY7C1049BN-15VC | 512K x 8 Static RAM |
| CY7C1049BN-15VI | 512K x 8 Static RAM |
| CY7C1049BN-15VXC | 512K x 8 Static RAM |
| CY7C1049BN-15VXI | 512K x 8 Static RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1049BN-15VC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1049BN-15VCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 4M-Bit 512K x 8 15ns 36-Pin SOJ T/R |
| CY7C1049BN-15VI | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1049BN-15VXC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY7C1049BN-15VXCT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Async Single 5V 4M-Bit 512K x 8 15ns 36-Pin SOJ T/R |
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