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參數(shù)資料
| 型號： | CY7C1012AV33-8BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 512K x 24 Static RAM |
| 中文描述： | 512K X 24 STANDARD SRAM, 8 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 175K |
| 代理商： | CY7C1012AV33-8BGI |
512K x 24 Static RAM
CY7C1012AV33
Cypress Semiconductor Corporation
Document #: 38-05254 Rev. *D
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised November 12, 2002
Features
High speed
—t
AA
= 8, 10, 12 ns
Low active power
—1080 mW (max.)
Operating voltages of 3.3 ± 0.3V
2.0V data retention
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE
0
, CE
1
and CE
2
features
Functional Description
The CY7C1012AV33 is a high-performance CMOS static RAM
organized as 512K words by 24 bits. Each data byte is
separately controlled by the individual chip selects (CE
0
, CE
1
,
CE
2
). CE
0
controls the data on the I/O
0
–
I/O
7
, while CE
1
controls the data on I/O
8
–
I/O
15
, and CE
2
controls the data on
the data pins I/O
16
–
I/O
23
. This device has an automatic
power-down feature that significantly reduces power
consumption when deselected.
Writing the data bytes into the SRAM is accomplished when
the chip select controlling that byte is LOW and the write
enable input (WE) input is LOW. Data on the respective
input/output (I/O) pins is then written into the location specified
on the address pins (A
0
–
A
18
). Asserting all of the chip selects
LOW and write enable LOW will write all 24 bits of data into
the SRAM. Output enable (OE) is ignored while in WRITE
mode.
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select
controlling that byte is LOW and write enable (WE) HIGH while
output enable (OE) remains LOW. Under these conditions, the
contents of the memory location specified on the address pins
will appear on the specified data input/output (I/O) pins.
Asserting all the chip selects LOW will read all 24 bits of data
from the SRAM.
The 24 I/O pins (I/O
0
–
I/O
23
) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
The CY7C1012AV33 is available in a standard 119-ball BGA.
Selection Guide
–
8
8
300
300
50
–
10
10
275
275
50
–
12
12
260
260
50
Unit
ns
mA
Maximum Access Time
Maximum Operating Current
Commercial
Industrial
Commercial/Industrial
Maximum CMOS Standby Current
mA
Functional Block Diagram
1
A
1
A
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
COLUMN
DECODER
R
S
INPUT BUFFER
512K x 24
ARRAY
4096 x 4096
A
0
A
1
A
1
A
1
A
1
A
1
A
1
A
1
I/O
0
–
I/O
7
OE
I/O
8
–
I/O
15
CE
0
, CE
1
, CE
2
WE
I/O
16
–
I/O
23
CONTROL LOGIC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1012CV33-12VXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1012CV33-15BAXI | 制造商:Cypress Semiconductor 功能描述: |
| CY7C1012DV33-10BGXI | 功能描述:靜態(tài)隨機(jī)存取存儲器 12-Mbit (512K x 24) 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1012DV33-10BGXIT | 功能描述:靜態(tài)隨機(jī)存取存儲器 12-Mbit (512K x 24) 靜態(tài)隨機(jī)存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| CY7C1012DV33-8BGXC | 制造商:Cypress Semiconductor 功能描述: |
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