參數(shù)資料
型號(hào)： CY7C1011
廠商： Cypress Semiconductor Corp.
英文描述： 128K x 16 Static RAM(128K x 16 靜態(tài) RAM)
中文描述： 128K的× 16靜態(tài)RAM（128K的× 16靜態(tài)RAM）的
文件頁(yè)數(shù)： 1/7頁(yè)
文件大?。?/td> 193K
代理商： CY7C1011
PRELIMINARY
128K x 16 Static RAM
CY7C1011
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
November 19, 1998
Features
High speed
—t
AA
= 15 ns
Low active power
—1150 mW (max.)
Low CMOS standby power (L version)
—40 mW (max.)
2.0V Data Retention (4 mW at 2.0V retention)
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE and OE features
Functional Description
The CY7C1011 is a high-performance CMOS static RAM or-
ganized as 131,072 words by 16 bits.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If byte high enable (BHE) is LOW, then data from
I/O pins (I/O
8
through I/O
15
) is written into the location speci-
fied on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O
0
to I/O
7
. If byte high enable (BHE) is LOW, then
data from memory will appear on I/O
8
to I/O
15
. See the truth
table at the back of this datasheet for a complete description
of read and write modes.
The input/output pins (I/O
0
through I/O
15
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1011 is available in a standard 44-pin TSOP II pack-
age with center power and ground (revolutionary) pinout.
1
A
1
A
Logic Block Diagram
Pin Configuration
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
R
S
INPUT BUFFER
256K x 16
ARRAY
1024 x 4096
A
0
A
1
A
1
A
1
A
1
1011–2
A
9
A
1
I/O
0
– I/O
7
BLE
I/O
8
– I/O
15
OE
WE
WE
A
16
A
15
A
14
A
13
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31
30
32
36
35
34
33
37
40
39
38
Top View
41
44
43
42
16
17
29
28
V
CC
V
SS
I/O
4
I/O
5
A
4
A
3
A
2
A
1
A
0
OE
BHE
BLE
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
5
A
6
A
7
I/O
15
I/O
14
I/O
13
I/O
12
CE
I/O
0
I/O
1
I/O
2
I/O
3
18
19
20
21
27
26
25
24
22
23
I/O
6
I/O
7
A
8
A
9
A
10
A
11
NC
1011–1
TSOP II
Selection Guide
7C1011-15
15
230
8
7C1011-20
20
220
8
7C1011-25
25
200
8
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Com’l
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