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參數(shù)資料
| 型號： | CY7B9930V-2AC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | High-Speed Multi-Frequency PLL Clock Buffer |
| 中文描述： | 7B SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP44 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 151K |
| 代理商： | CY7B9930V-2AC |
High-Speed Multi-Frequency PLL Clock Buffer
RoboClockII Junior
CY7B9930V
CY7B9940V
Cypress Semiconductor Corporation
Document #: 38-07271 Rev. *B
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised July 25, 2002
Features
12–100 MHz (CY7B9930V), or 24–200 MHz (CY7B9940V)
input/output operation
Matched pair output skew < 200 ps
Zero input-to-output delay
10 LVTTL 50% duty-cycle outputs capable of driving
50
ω
terminated lines
Commercial temp. range with eight outputs at 200 MHz
Industrial temp. range with eight outputs at 200 MHz
3.3V LVTTL/LV differential (LVPECL), fault-tolerant and
hot insertable reference inputs
Multiply ratios of (1–6, 8, 10, 12)
Operation up to 12x input frequency
Individual output bank disable for aggressive power
management and EMI reduction
Output high-impedance option for testing purposes
Fully integrated PLL with lock indicator
Low cycle-to-cycle jitter (<100 ps peak-peak)
Single 3.3V ± 10% supply
44-pin TQFP package
Functional Description
The CY7B9930V and CY7B9940V High-Speed Multi-
Frequency PLL Clock Buffers offer user-selectable control
over system clock functions. This multiple-output clock driver
provides the system integrator with functions necessary to
optimize the timing of high-performance computer or commu-
nication systems.
Ten configurable outputs can each drive terminated trans-
mission lines with impedances as low as 50
while delivering
minimal and specified output skews at LVTTL levels. The outputs
are arranged in three banks. The FB feedback bank consists
of two outputs, which allows divide-by functionality from 1 to
12. Any one of these ten outputs can be connected to the
feedback input as well as driving other inputs.
Selectable reference input is a fault tolerance feature that
allows smooth change over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs are configurable to accommodate both LVTTL or Differ-
ential (LVPECL) inputs. The completely integrated PLL
reduces jitter and simplifies board layout.
3
3
3
3
FS
Output_Mode
FBDS0
FBDS1
DIS2
DIS1
QFA0
QFA1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
LOCK
FBKA
REFA+
REFA–
REFB+
REFB–
REFSEL
Divide
Matrix
Phase
Freq.
Detector
Filter
VCO
Control Logic
Divide
Generator
Feedback Bank
Bank 2
Bank 1
1
2
3
36 35 34
37
38
39
40
41
42
43
44
25
24
23
26
27
28
33
32
31
30
29
VCCQ
REFA+
REFA –
REFSEL
REFB–
REFB+
DIS1
GND
DIS2
VCCQ
FS
GND
2QB1
VCCN
2QB0
GND
GND
GND
VCCN
GND
2QA0
2QA1
9
10
11
8
7
6
4
5
L
F
F
G
Q
V
V
G
F
G
Q
20
21 22
1
V
O
G
1
G
G
1
V
1
G
19
18
17
16
15
14
13
12
CY7B9930V/40V
44-Pin TQFP
Pin Configuration
Functional Block Diagram
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7B9930V-2AI | High-Speed Multi-Frequency PLL Clock Buffer |
| CY7B9930V-5AC | High-Speed Multi-Frequency PLL Clock Buffer |
| CY7B9930V-5AI | High-Speed Multi-Frequency PLL Clock Buffer |
| CY7B993V-2AC | High-Speed Multi-Phase PLL Clock Buffer |
| CY7B993V-5AC | High-Speed Multi-Phase PLL Clock Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7B9930V-2AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High Speed Multifrequency PLL Clock Buffer |
| CY7B9930V-5AC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High Speed Multifrequency PLL Clock Buffer |
| CY7B9930V-5AI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:High Speed Multifrequency PLL Clock Buffer |
| CY7B9930V-5AXC | 功能描述:鎖相環(huán) - PLL 3.3V 100MHz 10 COM Not Programable RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CY7B9930V-5AXCKJ | 制造商:Cypress Semiconductor 功能描述: |
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